1. Introduction

1.1. Purpose

This documents aims at defining the requirements for ECAP5-DWBMMSC as well as describing its architecture. Both user and product requirements will be covered.

1.2. Intended Audience and Use

This document targets hardware engineers who shall implement ECAP5-DWBMMSC by refering to the described architecture. It is also intended for system engineers working on the integration of ECAP5-DWBMMSC in ECAP5. Finally, this document shall be used as a technical reference by software engineers configuring ECAP5-DWBMMSC through hardware-software interfaces.

1.3. Product Scope

ECAP5-DWBMMSC is Wishbone memory-mapped single-cycle interface module

1.4. Conventions

1.4.1. Requirement format

This document details requirements with the following format :

Sample requirement

ID	Requirement_ID
Description	Requirement description
Rationale	Requirement rationale
DerivedFrom	Other_Requirement_ID

with requirement IDs having the following format :

• U_*: User requirements

• I_*: External interface requirements

• F_*: Functional requirements

• N_*: Non-Functional requirements

• A_*: Architecture requirements

The requirement hierarchy and traceability scheme is detailed in the following figure.

Requirement hierarchy and traceability

1.5. Definitions and Abbreviations

1.6. References

Date	Version	Title
June 22, 2010	B.4	WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores