2. Overall Description

2.1. User needs

ECAP5 is the primary user for ECAP5-DWBSPI, but it could be used as a standalone Wishbone UART peripheral as well.

ID	U_REGISTERS_01
Description	The peripheral shall provide memory-mapped configuration and status registers.

ID	U_MEMORY_INTERFACE_01
Description	The peripheral memory-mapped registers shall be accessible through a memory interface compliant with the Wishbone specification.

Wishbone Datasheet for the memory interface
Description	Specification
Revision level of the WISHBONE specification	B4
Type of interface	SLAVE
Signal names for the WISHBONE interface	Wishbone signals are prefixed with `wb_`.
ERR_I support	No
RTY_I support	No
Supported tags	None
Port size	32-bit
Port granularity	8-bit
Maximum operand size	32-bit
Data transfer ordering	Little Endian
Sequence of data transfer	Undefined
Clock constraints	Clocked on clk_i

N/A