3. Requirements

3.1. External Interface Requirements

Control signals

Name	Type	Width	Description
clk_i	I	1	Clock input.
rst_i	I	1	Hardware reset.

Memory interface signals

Name	Type	Width	Description
wb_adr_i	I	32	The address output array is used to pass binary address.
wb_dat_i	I	32	The data input array is used to pass binary data.
wb_dat_o	O	32	The data output array is used to pass binary data.
wb_sel_i	I	4	The select output array indicates where valid data is expected on the wb_dat_i signal array during READ cycles, and where it is placed on the wb_dat_o signal array during WRITE cycles. Each individual select signal correlates to one of four active bytes on the 32-bit data port.
wb_we_i	I	1	The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. This signal is negated during READ cycles and is asserted during WRITE cycles.
wb_stb_i	I	1	The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface.
wb_ack_o	O	1	The acknowledge input, when asserted, indicates the normal termination of a bus cycle.
wb_cyc_i	I	1	The cycle output, when asserted, indicates that a valid bus cycle is in progress. This signal is asserted for the duration of all bus cycles.
wb_stall_o	O	1	The stall input indicates that current slave is not able to accept the transfer in the transaction queue.

3.2. Functional Requirements

3.2.1. Memory interface

3.2.1.1. Wishbone protocol

The following requirements are extracted from the Wishbone specification.

ID	F_WISHBONE_DATASHEET_01
Description	The memory interface shall comply with the Wishbone Datasheet provided in section 2.1.
Derived from	U_MEMORY_INTERFACE_01

ID	F_WISHBONE_RESET_01
Description	The memory interface shall initialize itself at the rising edge of clk_i following the assertion of rst_i.
Derived from	U_MEMORY_INTERFACE_01

ID	F_WISHBONE_RESET_02
Description	The memory interface shall stay in the initialization state until the rising edge of clk_i following the deassertion of rst_i.
Derived from	U_MEMORY_INTERFACE_01

ID	F_WISHBONE_TRANSFER_CYCLE_01
Description	The memory interface shall only respond to transfer cycles when wb_cyc_i is asserted.
Derived from	U_MEMORY_INTERFACE_01

ID	F_WISHBONE_HANDSHAKE_01
Description	The memory interface shall assert the wb_ack_o signal in response to the logical AND of wb_cyc_i and wb_stb_i.
Derived from	U_MEMORY_INTERFACE_01

ID	F_WISHBONE_READ_CYCLE_01
Description	The memory interface shall conform to the READ cycle detailed in the figure below.
Derived from	U_MEMORY_INTERFACE_01

Timing diagram of the wishbone read cycle

ID	F_WISHBONE_WRITE_CYCLE_01
Description	The memory interface shall conform to the WRITE cycle detailed in figure below.
Derived from	U_MEMORY_INTERFACE_01

Timing diagram of the wishbone write cycle

ID	F_WISHBONE_TIMING_01
Description	The clock input clk_i shall coordinate all activites for the internal logic within the memory interface. All output signals of the memory interface shall be registered at the rising edge of clk_i. All input signals of the memory interface shall be stable before the rising edge of clk_i.
Rationale	As long as the memory interface is designed within the clock domain of clk_i, the requirement will be satisfied by using the place and route tool.
Derived from	U_MEMORY_INTERFACE_01

3.2.1.2. Memory-mapped registers

ID	F_REGISTERS_01
Description	The following registers shall be implemented and accessible through the wishbone memory interface.
Derived from	U_REGISTERS_01 U_MEMORY_INTERFACE_01 U_BAUD_RATE_01 U_PARITY_BIT_01 U_DATA_SIZE_01 U_STOP_BIT_01

Address Offset	Register name	Width (in bits)	Access	Reset value	Section/page
0000_0000h	Status register (SPI_SR)	32	R	0000_0000h	SPI_SR
0000_0004h	Control register (SPI_CR)	32	R/W	0000_0000h	SPI_CR
0000_0008h	Receive Data register (SPI_RXDR)	32	R	0000_0000h	SPI_RXDR
0000_000Ch	Transmit Data register (SPI_TXDR)	32	W	0000_0000h	SPI_TXDR

3.2.1.2.1. Status register (SPI_SR)

Position	Field	Description
31-1	Reserved	This field is reserved. This read-only field is reserved and always has the value 0.
0	TXE	Transmit register Empty 0   The transmit register is full (being sent) 1   The transmit register is empty

3.2.1.2.2. Control register (SPI_CR)

SPI_CR contains the control for selecting the SPI frequency and controlling the chip select.

Position	Field	Description
31-16	Prescaler	SPI frequency selector The specified SPI frequency is f_spi = (f_sys / (2 * prescaler)).
15-1	reserved	This field is reserved. This read-only field is reserved and always has the value 0.
0	CS	Active-high Chip select 0   Chip-select disabled 1   Chip-select enabled

3.2.1.2.3. Receive Data register (SPI_RXDR)

Position	Field	Description
31-8	reserved	This field is reserved. This read-only field is reserved and always has the value 0.
7-0	RXD	Receive Data The received data is written to this field. The field is cleared by hardware after being read.

3.2.1.2.4. Transmit Data register (SPI_TXDR)

Position	Field	Description
31-8	reserved	This field is reserved.
7-0	TXD	Transmit Data Data written to this field is sent through the serial link. The TXE field of the SPI_SR shall be sample before writing again to this field to prevent data loss.

3.3. Non-functional Requirements

N/A