3. Requirements
3.1. External Interface Requirements
Name |
Type |
Width |
Description |
|---|---|---|---|
clk_i |
I |
1 |
Clock input. |
rst_i |
I |
1 |
Hardware reset. |
| ID | I_CLK_01 |
| Description | ECAP5-DPROC’s outputs shall be registered on the rising edge of clk_i. |
| ID | I_RESET_01 |
| Description | The rst_i signal shall hold ECAP5-DPROC in a reset state while asserted. |
| Derived from |
Name |
Type |
Width |
Description |
|---|---|---|---|
wb_adr_o |
O |
32 |
The address output array is used to pass binary address. |
wb_dat_i |
I |
32 |
The data input array is used to pass binary data. |
wb_dat_o |
O |
32 |
The data output array is used to pass binary data. |
wb_sel_o |
O |
4 |
The select output array indicates where valid data is expected on the wb_dat_i signal array during READ cycles, and where it is placed on the wb_dat_o signal array during WRITE cycles. Each individual select signal correlates to one of four active bytes on the 32-bit data port. |
wb_we_o |
O |
1 |
The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. This signal is negated during READ cycles and is asserted during WRITE cycles. |
wb_stb_o |
O |
1 |
The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface. |
wb_ack_i |
I |
1 |
The acknowledge input, when asserted, indicates the normal termination of a bus cycle. |
wb_cyc_o |
O |
1 |
The cycle output, when asserted, indicates that a valid bus cycle is in progress. This signal is asserted for the duration of all bus cycles. |
wb_stall_i |
O |
1 |
The pipeline stall input indicates that current slave is not able to accept the transfer in the transaction queue. |
3.2. Functional Requirements
3.2.1. Register file
| ID | F_REGISTER_01 |
| Description | ECAP5-DPROC shall implement 32 user-accessible general purpose registers ranging from x0 to x31. |
| Derived from |
| ID | F_REGISTER_02 |
| Description | Register x0 shall always be equal to zero. |
| Derived from |
| ID | F_REGISTER_03 |
| Description | ECAP5-DPROC shall implement a pc register storing the address of the current instruction. |
| Derived from |
| ID | F_REGISTER_RESET_01 |
| Description | The pc register shall be loaded with an hardware-configurable address when ECAP5-DPROC leaves its reset state. |
| Derived from |
3.2.2. Instruction decoding
The following figure outlines the different instruction encodings for the RV32I instruction set. The instruction encoding is infered from the opcode as there can only be one encoding per opcode.
RISC-V instruction encodings
3.2.3. Immediate encoding
Only one immediate value can be encoded in one instruction. The value can be reconstructed from fragments of the following format : imm[x] representing the x th bit or imm[x:y] representing bits from the xth to the yth both included.
| ID | F_INSTR_IMMEDIATE_01 |
| Description | Immediate values shall be sign-extended. |
| Derived from |
| ID | F_INSTR_IMMEDIATE_02 |
| Description | The value of an instruction immediate shall be the concatenation of immediate fragments from the instruction encoding. |
| Derived from |
| ID | F_INSTR_IMMEDIATE_03 |
| Description | Missing immediate fragments shall be replaced by zeros. |
| Derived from |
3.2.4. Opcodes
The following table outlines the different opcodes values of the RV32I instruction set.
RISC-V instruction opcodes
Note
Cells marked as noimp are for opcodes that are not implemented in version 1.0.0.
| ID | F_OPCODE_ENCODING_01 |
| Description | Instructions with the following opcodes shall be decoded as an R-type instruction : OP. |
| Derived from |
| ID | F_OPCODE_ENCODING_02 |
| Description | Instructions with the following opcodes shall be decoded as an I-type instruction : JALR, LOAD, OP-IMM, MISC-MEM and SYSTEM. |
| Derived from |
| ID | F_OPCODE_ENCODING_03 |
| Description | Instructions with the following opcodes shall be decoded as an S-type instruction : STORE. |
| Derived from |
| ID | F_OPCODE_ENCODING_04 |
| Description | Instructions with the following opcodes shall be decoded as an B-type instruction : BRANCH. |
| Derived from |
| ID | F_OPCODE_ENCODING_05 |
| Description | Instructions with the following opcodes shall be decoded as an U-type instruction : LUI and AUIPC. |
| Derived from |
| ID | F_OPCODE_ENCODING_06 |
| Description | Instructions with the following opcodes shall be decoded as an J-type instruction : JAL. |
| Derived from |
3.2.5. Instruction behaviors
3.2.5.1. LUI
| ID | F_LUI_01 |
| Description | When the opcode is LUI, the register pointed by the rd field shall be loaded with the immediate value. |
| Rationale | The LUI instruction shall load the 20 upper bits of the instruction immediate into the destination register and fill the remaining bits with zeros. This is the default behavior for instruction immediates as stated in F_INSTR_IMMEDIATE_02 and F_INSTR_IMMEDIATE_03. |
| Derived from |
3.2.5.2. AUIPC
| ID | F_AUIPC_01 |
| Description | When the opcode is AUIPC, the register pointed by the rd field shall be the signed sum of the immediate value and the address of the instruction. |
| Derived from |
3.2.5.3. JAL
| ID | F_JAL_01 |
| Description | When the opcode is JAL, the pc register shall be loaded with the signed sum of the immediate value and the address of the instruction. |
| Derived from |
| ID | F_JAL_02 |
| Description | When the opcode is JAL, the register pointed by the rd field shall be loaded with the address of the instruction incremented by 4. |
| Rationale | The JAL instruction shall output the address to the following instruction for it to be used as a *return address* in the case of a function call. |
| Derived from |
3.2.5.4. JALR
| ID | F_JALR_01 |
| Description | When the opcode is JALR and the func3 field is 0x0, the pc register shall be loaded with the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
| ID | F_JALR_02 |
| Description | When the opcode is JALR and the func3 field is 0x0, the register pointed by the rd field shall be loaded with the address of the instruction incremented by 4. |
| Rationale | The JALR instruction shall output the address to the following instruction for it to be used as a *return address* in the case of a function call. |
| Derived from |
3.2.5.5. BEQ
| ID | F_BEQ_01 |
| Description | When the opcode is BRANCH and the func3 field is 0x0, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the registers pointed by the rs1 field and the rs2 field are equal. |
| Derived from |
3.2.5.6. BNE
| ID | F_BNE_01 |
| Description | When the opcode is BRANCH and the func3 field is 0x1, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the registers pointed by the rs1 field and the rs2 field are equal. |
| Derived from |
3.2.5.7. BLT
| ID | F_BLT_01 |
| Description | When the opcode is BRANCH and the func3 field is 0x4, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using a signed comparison. |
| Derived from |
3.2.5.8. BGE
| ID | F_BGE_01 |
| Description | When the opcode is BRANCH and the func3 field is 0x5, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is greater than the register pointed by the rs2 field using a signed comparison. |
| Derived from |
3.2.5.9. BLTU
| ID | F_BLTU_01 |
| Description | When the opcode is BRANCH and the func3 field is 0x6, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using an unsigned comparison. |
| Derived from |
3.2.5.10. BGEU
| ID | F_BGEU_01 |
| Description | When the opcode is BRANCH and the func3 field is 0x7, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is greater than the register pointed by the rs2 field using an unsigned comparison. |
| Derived from |
3.2.5.11. LB
| ID | F_LB_01 |
| Description | When the opcode is LOAD and the func3 field is 0x0, the register pointed by the rd field shall be the 32 bits sign-extended 8-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.12. LH
| ID | F_LH_01 |
| Description | When the opcode is LOAD and the func3 field is 0x1, the register pointed by the rd field shall be the 32 bits sign-extended 16-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.13. LW
| ID | F_LW_01 |
| Description | When the opcode is LOAD and the func3 field is 0x2, the register pointed by the rd field shall be the 32-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.14. LBU
| ID | F_LBU_01 |
| Description | When the opcode is LOAD and the func3 field is 0x4, the register pointed by the rd field shall be the 32 bits zero-extended 8-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.15. LHU
| ID | F_LHU_01 |
| Description | When the opcode is LOAD and the func3 field is 0x5, the register pointed by the rd field shall be the 32 bits zero-extended 16-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.16. SB
| ID | F_SB_01 |
| Description | When the opcode is STORE and the func3 field is 0x0, the least-significant byte of the register pointed by the rs2 field shall be stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.17. SH
| ID | F_SH_01 |
| Description | When the opcode is STORE and the func3 field is 0x1, the two least-significant bytes of the register pointed by the rs2 field shall be stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.18. SW
| ID | F_SW_01 |
| Description | When the opcode is STORE and the func3 field is 0x2, the register pointed by the rs2 field shall be stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.19. ADDI
| ID | F_ADDI_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x0, the register pointed by the rd field shall be loaded with the signed sum of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.20. SLTI
| ID | F_SLTI_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x1, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the immediate value using a signed comparison, 0 otherwise. |
| Derived from |
3.2.5.21. SLTIU
| ID | F_SLTIU_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x3, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the immediate value using an unsigned comparison, 0 otherwise. |
| Derived from |
3.2.5.22. XORI
| ID | F_XORI_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x4, the register pointed by the rd field shall be the result of a bitwise xor of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.23. ORI
| ID | F_ORI_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x6, the register pointed by the rd field shall be the result of a bitwise or of the register pointed by the rs1 field and the immediate value. |
| Derived from |
3.2.5.24. ANDI
| ID | F_ANDI_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x7, the register pointed by the rd field shall be the result of a bitwise and of the register pointed by the rs1 field and immediate value. |
| Derived from |
3.2.5.25. SLLI
| ID | F_SLLI_01 |
| Description | When the opcode is OP-IMM and the func3 field is 0x1, the register pointed by the rd field shall be the register pointed by the rs1 field shited left by the number of bits specified in the 5 lowest-significant bits of the immediate value, filling lower bits with zeros. |
| Derived from |
3.2.5.26. SRLI
| ID | F_SRLI_01 |
| Description | When the opcode is OP-IMM, the func3 field is 0x5 and the 30th bit of the immediate value is 0, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified in the 5 lowest-significant bits of the immediate value, filling upper bits with zeros. |
| Derived from |
3.2.5.27. SRAI
| ID | F_SRAI_01 |
| Description | When the opcode is OP-IMM, the func3 field is 0x5 and the 30th bit of the immediate value is 1, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified in the 5 lowest-significant bits of the immediate value, filling upper bits with the most-significant bit of the register pointed by the rs1 field. |
| Derived from |
3.2.5.28. ADD
| ID | F_ADD_01 |
| Description | When the opcode is OP, the func3 field is 0x0 and the func7 field is 0x0, the register pointed by the rd field shall be the signed sum of the registers pointed by the rs1 and rs2 fields. |
| Derived from |
3.2.5.29. SUB
| ID | F_SUB_01 |
| Description | When the opcode is OP, the func3 field is 0x0 and the func7 field is 0x20, the register pointed by the rd field shall be the difference of the register pointed by the rs1 field minus the register pointed by the rs2 fields. |
| Derived from |
3.2.5.30. SLT
| ID | F_SLT_01 |
| Description | When the opcode is OP and the func3 field is 0x2, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using a signed comparison, 0 otherwise. |
| Derived from |
3.2.5.31. SLTU
| ID | F_SLTU_01 |
| Description | When the opcode is OP and the func3 field is 0x3, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using an unsigned comparison, 0 otherwise. |
| Derived from |
3.2.5.32. XOR
| ID | F_XOR_01 |
| Description | When the opcode is OP and the func3 field is 0x4, the register pointed by the rd field shall be the result of a bitwise xor of the registers pointed by the rs1 and rs2 fields. |
| Derived from |
3.2.5.33. OR
| ID | F_OR_01 |
| Description | When the opcode is OP and the func3 field is 0x6, the register pointed by the rd field shall be the result of a bitwise or of the registers pointed by the rs1 and rs2 fields. |
| Derived from |
3.2.5.34. AND
| ID | F_AND_01 |
| Description | When the opcode is OP and the func3 field is 0x7, the register pointed by the rd field shall be the result of a bitwise and of the registers pointed by the rs1 and rs2 fields. |
| Derived from |
3.2.5.35. SLL
| ID | F_SLL_01 |
| Description | When the opcode is OP and the func3 field is 0x1, the register pointed by the rd field shall be the register pointed by the rs1 field shited left by the number of bits specified by the register pointed by the rs2 field, filling lower bits with zeros. |
| Derived from |
3.2.5.36. SRL
| ID | F_SRL_01 |
| Description | When the opcode is OP, the func3 field is 0x5 and the func7 field is 0x0, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified by the register pointed by the rs2 field, filling upper bits with zeros. |
| Derived from |
3.2.5.37. SRA
| ID | F_SRA_01 |
| Description | When the opcode is OP, the func3 field is 0x5 and the func7 field is 0x0, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified in the register pointed by the rs2 field, filling upper bits with the most-significant bit of the register pointed by the rs1 field. |
| Derived from |
3.2.5.38. FENCE
Warning
The FENCE instructions are scoped for version 1.0.0 but are not implemented in version 1.0.0-alpha1.
3.2.5.39. ECALL
Warning
The ECALL instruction is scoped for version 1.0.0 but is not implemented in version 1.0.0-alpha1.
3.2.5.40. EBREAK
Warning
The EBREAK instruction is scoped for version 1.0.0 but is not implemented in version 1.0.0-alpha1.
3.2.6. Exceptions
| ID | F_INSTR_ADDR_MISALIGNED_01 |
| Description | An Instruction Address Misaligned exception shall be raised when the target address of a taken branch or an unconditional jump is not four-byte aligned. |
| Derived from |
| ID | F_MISALIGNED_MEMORY_ACCESS_01 |
| Description | A Misaligned Memory Access exception shall be raised when the target address of a load/store instruction is not aligned on the referenced type size. |
| Derived from |
3.2.7. Memory interface
3.2.7.1. Memory accesses
| ID | F_MEMORY_INTERFACE_01 |
| Description | Both instruction and data accesses shall be handled by a unique external memory interface. |
| Derived from |
3.2.7.2. Wishbone protocol
The following requirements are extracted from the Wishbone specification.
| ID | F_WISHBONE_DATASHEET_01 |
| Description | The memory interface shall comply with the Wishbone Datasheet provided in section 2.1. |
| Derived from |
| ID | F_WISHBONE_RESET_01 |
| Description | The memory interface shall initialize itself at the rising edge of clk_i following the assertion of rst_i. |
| Derived from |
| ID | F_WISHBONE_RESET_02 |
| Description | The memory interface shall stay in the initialization state until the rising edge of clk_i following the deassertion of rst_i. |
| Derived from |
| ID | F_WISHBONE_RESET_03 |
| Description | Signals wb_stb_o and wb_cyc_o shall be deasserted while the memory interface is in the initialization state. The state of all other memory interface signals are undefined in response to a reset cycle. |
| Derived from |
| ID | F_WISHBONE_TRANSFER_CYCLE_01 |
| Description | The memory interface shall assert wb_cyc_o for the entire duration of the memory access. |
| Derived from |
| ID | F_WISHBONE_TRANSFER_CYCLE_02 |
| Description | Signal wb_cyc_o shall be asserted no later than the rising edge of clk_i that qualifies the assertion of wb_stb_o. |
| Derived from |
| ID | F_WISHBONE_TRANSFER_CYCLE_03 |
| Description | Signal wb_cyc_o shall be deasserted no earlier than the rising edge of clk_i that qualifies the deassertion of wb_stb_o. |
| Derived from |
| ID | F_WISHBONE_HANDSHAKE_02 |
| Description | The memory interface must qualify the following signals with wb_stb_o : wb_adr_o, wb_dat_o, wb_sel_o and wb_we_o. |
| Derived from |
| ID | F_WISHBONE_STALL_01 |
| Description | While initiating a request, the memory interface shall hold the state of its outputs until wb_stall_i is deasserted. |
| Rationale | wb_stall_i is asserted to indicate that the request queue is temporary full and the request shall be resent. |
| Derived from |
| ID | F_WISHBONE_READ_CYCLE_01 |
| Description | A read transaction shall be started by asserting both wb_cyc_o and wb_stb_i, and deasserting wb_we_o. |
| Derived from |
| ID | F_WISHBONE_READ_CYCLE_02 |
| Description | The memory interface shall conform to the READ cycle detailed in the figure below. |
| Derived from |
Timing diagram of the wishbone read cycle
| ID | F_WISHBONE_WRITE_CYCLE_01 |
| Description | A write transaction shall be started by asserting wb_cyc_o, wb stb i and wb_we_o. |
| Derived from |
| ID | F_WISHBONE_WRITE_CYCLE_02 |
| Description | The memory interface shall conform to the WRITE cycle detailed in figure below. |
| Derived from |
Timing diagram of the wishbone write cycle
| ID | F_WISHBONE_TIMING_01 |
| Description | The clock input clk_i shall coordinate all activites for the internal logic within the memory interface. All output signals of the memory interface shall be registered at the rising edge of clk_i. All input signals of the memory interface shall be stable before the rising edge of clk_i. |
| Rationale | As long as the memory interface is designed within the clock domain of clk_i, the requirement will be satisfied by using the place and route tool. |
| Derived from |
Note
BLOCK cycles are not supported in version 1.0.0
3.2.7.3. Caches
Note
Caches are not supported in version 1.0.0
3.2.8. Debugging
Warning
RISC-V Debug Support is scoped for version 1.0.0 but is not supported in version 1.0.0-alpha1.
3.3. Non-functional Requirements
N/A