Test and Traceability Report

Summary

🚫	Test report	99%
🚫	Traceability report	96%

Test report

	Success	Failure	Skipped	Unknown	Total
Tests	551	0	4	0	555

Run tests

Testsuite	Testcase	Check ID	Status
`tb_registers`	`read_x0`	`tb_registers.read_x0.01`	✅
	`read_port_a`	`tb_registers.read_port_a.01`	✅
	`read_port_b`	`tb_registers.read_port_b.01`	✅
	`write_x0`	`tb_registers.write_x0.01`	✅
	`write`	`tb_registers.write.01`	✅
	`parallel_read`	`tb_registers.parallel_read.01`	✅
	`read_before_write`	`tb_registers.read_before_write.01`	✅
`tb_loadstore`	`reset`	`tb_loadstore.reset.01`	✅
	`reset`	`tb_loadstore.reset.02`	✅
	`no_stall`	`tb_loadstore.no_stall.LB_01`	✅
		`tb_loadstore.no_stall.LB_02`	✅
		`tb_loadstore.no_stall.LB_03`	✅
		`tb_loadstore.no_stall.LB_04`	✅
		`tb_loadstore.no_stall.LB_05`	✅
		`tb_loadstore.no_stall.LBU_01`	✅
		`tb_loadstore.no_stall.LBU_02`	✅
		`tb_loadstore.no_stall.LBU_03`	✅
		`tb_loadstore.no_stall.LBU_04`	✅
		`tb_loadstore.no_stall.LBU_05`	✅
		`tb_loadstore.no_stall.LH_01`	✅
		`tb_loadstore.no_stall.LH_02`	✅
		`tb_loadstore.no_stall.LH_03`	✅
		`tb_loadstore.no_stall.LH_04`	✅
		`tb_loadstore.no_stall.LH_05`	✅
		`tb_loadstore.no_stall.LHU_01`	✅
		`tb_loadstore.no_stall.LHU_02`	✅
		`tb_loadstore.no_stall.LHU_03`	✅
		`tb_loadstore.no_stall.LHU_04`	✅
		`tb_loadstore.no_stall.LHU_05`	✅
		`tb_loadstore.no_stall.LW_01`	✅
		`tb_loadstore.no_stall.LW_02`	✅
		`tb_loadstore.no_stall.LW_03`	✅
		`tb_loadstore.no_stall.LW_04`	✅
		`tb_loadstore.no_stall.LW_05`	✅
		`tb_loadstore.no_stall.SB_01`	✅
		`tb_loadstore.no_stall.SB_02`	✅
		`tb_loadstore.no_stall.SB_03`	✅
		`tb_loadstore.no_stall.SB_04`	✅
		`tb_loadstore.no_stall.SB_05`	✅
		`tb_loadstore.no_stall.SH_01`	✅
		`tb_loadstore.no_stall.SH_02`	✅
		`tb_loadstore.no_stall.SH_03`	✅
		`tb_loadstore.no_stall.SH_04`	✅
		`tb_loadstore.no_stall.SH_05`	✅
		`tb_loadstore.no_stall.SW_01`	✅
		`tb_loadstore.no_stall.SW_02`	✅
		`tb_loadstore.no_stall.SW_03`	✅
		`tb_loadstore.no_stall.SW_04`	✅
		`tb_loadstore.no_stall.SW_05`	✅
	`memory_stall`	`tb_loadstore.memory_stall.01`	✅
		`tb_loadstore.memory_stall.02`	✅
		`tb_loadstore.memory_stall.03`	✅
	`memory_wait`	`tb_loadstore.memory_wait.01`	✅
		`tb_loadstore.memory_wait.02`	✅
		`tb_loadstore.memory_wait.03`	✅
	`bypass`	`tb_loadstore.bypass.01`	✅
		`tb_loadstore.bypass.02`	✅
		`tb_loadstore.bypass.03`	✅
	`bubble`	`tb_loadstore.bubble.01`	✅
		`tb_loadstore.bubble.02`	✅
		`tb_loadstore.bubble.03`	✅
	`back_to_back`	`tb_loadstore.back_to_back.01`	✅
	`back_to_back`	`tb_loadstore.back_to_back.02`	✅
`riscv-tests`	`simple`	`riscv-tests.simple.01`	✅
	`simple`	`riscv-tests.simple.02`	✅
	`add`	`riscv-tests.add.01`	✅
	`add`	`riscv-tests.add.02`	✅
	`addi`	`riscv-tests.addi.01`	✅
	`addi`	`riscv-tests.addi.02`	✅
	`and`	`riscv-tests.and.01`	✅
	`and`	`riscv-tests.and.02`	✅
	`andi`	`riscv-tests.andi.01`	✅
	`andi`	`riscv-tests.andi.02`	✅
	`auipc`	`riscv-tests.auipc.01`	✅
	`auipc`	`riscv-tests.auipc.02`	✅
	`beq`	`riscv-tests.beq.01`	✅
	`beq`	`riscv-tests.beq.02`	✅
	`bge`	`riscv-tests.bge.01`	✅
	`bge`	`riscv-tests.bge.02`	✅
	`bgeu`	`riscv-tests.bgeu.01`	✅
	`bgeu`	`riscv-tests.bgeu.02`	✅
	`blt`	`riscv-tests.blt.01`	✅
	`blt`	`riscv-tests.blt.02`	✅
	`bltu`	`riscv-tests.bltu.01`	✅
	`bltu`	`riscv-tests.bltu.02`	✅
	`bne`	`riscv-tests.bne.01`	✅
	`bne`	`riscv-tests.bne.02`	✅
	`jal`	`riscv-tests.jal.01`	✅
	`jal`	`riscv-tests.jal.02`	✅
	`jalr`	`riscv-tests.jalr.01`	✅
	`jalr`	`riscv-tests.jalr.02`	✅
	`lb`	`riscv-tests.lb.01`	✅
	`lb`	`riscv-tests.lb.02`	✅
	`lbu`	`riscv-tests.lbu.01`	✅
	`lbu`	`riscv-tests.lbu.02`	✅
	`lh`	`riscv-tests.lh.01`	✅
	`lh`	`riscv-tests.lh.02`	✅
	`lhu`	`riscv-tests.lhu.01`	✅
	`lhu`	`riscv-tests.lhu.02`	✅
	`lw`	`riscv-tests.lw.01`	✅
	`lw`	`riscv-tests.lw.02`	✅
	`lui`	`riscv-tests.lui.01`	✅
	`lui`	`riscv-tests.lui.02`	✅
	`or`	`riscv-tests.or.01`	✅
	`or`	`riscv-tests.or.02`	✅
	`ori`	`riscv-tests.ori.01`	✅
	`ori`	`riscv-tests.ori.02`	✅
	`sb`	`riscv-tests.sb.01`	✅
	`sb`	`riscv-tests.sb.02`	✅
	`sh`	`riscv-tests.sh.01`	✅
	`sh`	`riscv-tests.sh.02`	✅
	`sw`	`riscv-tests.sw.01`	✅
	`sw`	`riscv-tests.sw.02`	✅
	`sll`	`riscv-tests.sll.01`	✅
	`sll`	`riscv-tests.sll.02`	✅
	`slli`	`riscv-tests.slli.01`	✅
	`slli`	`riscv-tests.slli.02`	✅
	`slt`	`riscv-tests.slt.01`	✅
	`slt`	`riscv-tests.slt.02`	✅
	`slti`	`riscv-tests.slti.01`	✅
	`slti`	`riscv-tests.slti.02`	✅
	`sltiu`	`riscv-tests.sltiu.01`	✅
	`sltiu`	`riscv-tests.sltiu.02`	✅
	`sltu`	`riscv-tests.sltu.01`	✅
	`sltu`	`riscv-tests.sltu.02`	✅
	`sra`	`riscv-tests.sra.01`	✅
	`sra`	`riscv-tests.sra.02`	✅
`srai`	`riscv-tests.srai.01`	✅
`srai`	`riscv-tests.srai.02`	✅
`srl`	`riscv-tests.srl.01`	✅
`srl`	`riscv-tests.srl.02`	✅
`srli`	`riscv-tests.srli.01`	✅
`srli`	`riscv-tests.srli.02`	✅
`sub`	`riscv-tests.sub.01`	✅
`sub`	`riscv-tests.sub.02`	✅
`xor`	`riscv-tests.xor.01`	✅
`xor`	`riscv-tests.xor.02`	✅
`xori`	`riscv-tests.xori.01`	✅
`xori`	`riscv-tests.xori.02`	✅
`tb_writeback`	`write`	`tb_writeback.write.01`	✅
	`bypass`	`tb_writeback.bypass.01`	✅
	`bubble`	`tb_writeback.bubble.01`	✅
`tb_decode`	`reset`	`tb_decode.reset.01`	✅
	`lui`	`tb_decode.lui.01`	✅
		`tb_decode.lui.02`	✅
		`tb_decode.lui.03`	✅
		`tb_decode.lui.04`	✅
		`tb_decode.lui.05`	✅
	`auipc`	`tb_decode.auipc.01`	✅
		`tb_decode.auipc.02`	✅
		`tb_decode.auipc.03`	✅
		`tb_decode.auipc.04`	✅
		`tb_decode.auipc.05`	✅
	`jal`	`tb_decode.jal.01`	✅
		`tb_decode.jal.02`	✅
		`tb_decode.jal.03`	✅
		`tb_decode.jal.04`	✅
		`tb_decode.jal.05`	✅
	`jalr`	`tb_decode.jalr.01`	✅
		`tb_decode.jalr.02`	✅
		`tb_decode.jalr.03`	✅
		`tb_decode.jalr.04`	✅
		`tb_decode.jalr.05`	✅
	`beq`	`tb_decode.beq.01`	✅
		`tb_decode.beq.02`	✅
		`tb_decode.beq.03`	✅
		`tb_decode.beq.04`	✅
		`tb_decode.beq.05`	✅
		`tb_decode.beq.06`	✅
	`bne`	`tb_decode.bne.01`	✅
		`tb_decode.bne.02`	✅
		`tb_decode.bne.03`	✅
		`tb_decode.bne.04`	✅
		`tb_decode.bne.05`	✅
		`tb_decode.bne.06`	✅
	`blt`	`tb_decode.blt.01`	✅
		`tb_decode.blt.02`	✅
		`tb_decode.blt.03`	✅
		`tb_decode.blt.04`	✅
		`tb_decode.blt.05`	✅
		`tb_decode.blt.06`	✅
	`bge`	`tb_decode.bge.01`	✅
		`tb_decode.bge.02`	✅
		`tb_decode.bge.03`	✅
		`tb_decode.bge.04`	✅
		`tb_decode.bge.05`	✅
		`tb_decode.bge.06`	✅
	`bltu`	`tb_decode.bltu.01`	✅
		`tb_decode.bltu.02`	✅
		`tb_decode.bltu.03`	✅
		`tb_decode.bltu.04`	✅
		`tb_decode.bltu.05`	✅
		`tb_decode.bltu.06`	✅
	`bgeu`	`tb_decode.bgeu.01`	✅
		`tb_decode.bgeu.02`	✅
		`tb_decode.bgeu.03`	✅
		`tb_decode.bgeu.04`	✅
		`tb_decode.bgeu.05`	✅
		`tb_decode.bgeu.06`	✅
	`lb`	`tb_decode.lb.01`	✅
		`tb_decode.lb.02`	✅
		`tb_decode.lb.03`	✅
		`tb_decode.lb.04`	✅
		`tb_decode.lb.05`	✅
	`lbu`	`tb_decode.lbu.01`	✅
		`tb_decode.lbu.02`	✅
`tb_decode.lbu.03`		✅
`tb_decode.lbu.04`		✅
`tb_decode.lbu.05`		✅
`lh`	`tb_decode.lh.01`	✅
	`tb_decode.lh.02`	✅
	`tb_decode.lh.03`	✅
	`tb_decode.lh.04`	✅
	`tb_decode.lh.05`	✅
`lhu`	`tb_decode.lhu.01`	✅
	`tb_decode.lhu.02`	✅
	`tb_decode.lhu.03`	✅
	`tb_decode.lhu.04`	✅
	`tb_decode.lhu.05`	✅
`lw`	`tb_decode.lw.01`	✅
	`tb_decode.lw.02`	✅
	`tb_decode.lw.03`	✅
	`tb_decode.lw.04`	✅
	`tb_decode.lw.05`	✅
`sb`	`tb_decode.sb.01`	✅
	`tb_decode.sb.02`	✅
	`tb_decode.sb.03`	✅
	`tb_decode.sb.04`	✅
	`tb_decode.sb.05`	✅
`sh`	`tb_decode.sh.01`	✅
	`tb_decode.sh.02`	✅
	`tb_decode.sh.03`	✅
	`tb_decode.sh.04`	✅
	`tb_decode.sh.05`	✅
`sw`	`tb_decode.sw.01`	✅
	`tb_decode.sw.02`	✅
	`tb_decode.sw.03`	✅
	`tb_decode.sw.04`	✅
	`tb_decode.sw.05`	✅
`addi`	`tb_decode.addi.01`	✅
	`tb_decode.addi.02`	✅
	`tb_decode.addi.03`	✅
	`tb_decode.addi.04`	✅
	`tb_decode.addi.05`	✅
`slti`	`tb_decode.slti.01`	✅
	`tb_decode.slti.02`	✅
	`tb_decode.slti.03`	✅
	`tb_decode.slti.04`	✅
	`tb_decode.slti.05`	✅
`sltiu`	`tb_decode.sltiu.01`	✅
	`tb_decode.sltiu.02`	✅
	`tb_decode.sltiu.03`	✅
	`tb_decode.sltiu.04`	✅
	`tb_decode.sltiu.05`	✅
`xori`	`tb_decode.xori.01`	✅
	`tb_decode.xori.02`	✅
	`tb_decode.xori.03`	✅
	`tb_decode.xori.04`	✅
	`tb_decode.xori.05`	✅
`ori`	`tb_decode.ori.01`	✅
	`tb_decode.ori.02`	✅
	`tb_decode.ori.03`	✅
	`tb_decode.ori.04`	✅
	`tb_decode.ori.05`	✅
`andi`	`tb_decode.andi.01`	✅
	`tb_decode.andi.02`	✅
	`tb_decode.andi.03`	✅
	`tb_decode.andi.04`	✅
	`tb_decode.andi.05`	✅
`slli`	`tb_decode.slli.01`	✅
	`tb_decode.slli.02`	✅
	`tb_decode.slli.03`	✅
	`tb_decode.slli.04`	✅
	`tb_decode.slli.05`	✅
`srli`	`tb_decode.srli.01`	✅
	`tb_decode.srli.02`	✅
	`tb_decode.srli.03`	✅
	`tb_decode.srli.04`	✅
	`tb_decode.srli.05`	✅
`srai`	`tb_decode.srai.01`	✅
	`tb_decode.srai.02`	✅
	`tb_decode.srai.03`	✅
	`tb_decode.srai.04`	✅
	`tb_decode.srai.05`	✅
`add`	`tb_decode.add.01`	✅
	`tb_decode.add.02`	✅
	`tb_decode.add.03`	✅
	`tb_decode.add.04`	✅
	`tb_decode.add.05`	✅
`sub`	`tb_decode.sub.01`	✅
	`tb_decode.sub.02`	✅
	`tb_decode.sub.03`	✅
	`tb_decode.sub.04`	✅
	`tb_decode.sub.05`	✅
`slt`	`tb_decode.slt.01`	✅
	`tb_decode.slt.02`	✅
	`tb_decode.slt.03`	✅
	`tb_decode.slt.04`	✅
	`tb_decode.slt.05`	✅
`sltu`	`tb_decode.sltu.01`	✅
	`tb_decode.sltu.02`	✅
	`tb_decode.sltu.03`	✅
	`tb_decode.sltu.04`	✅
	`tb_decode.sltu.05`	✅
`xor`	`tb_decode.xor.01`	✅
	`tb_decode.xor.02`	✅
	`tb_decode.xor.03`	✅
	`tb_decode.xor.04`	✅
	`tb_decode.xor.05`	✅
`or`	`tb_decode.or.01`	✅
	`tb_decode.or.02`	✅
	`tb_decode.or.03`	✅
	`tb_decode.or.04`	✅
	`tb_decode.or.05`	✅
`and`	`tb_decode.and.01`	✅
	`tb_decode.and.02`	✅
	`tb_decode.and.03`	✅
	`tb_decode.and.04`	✅
	`tb_decode.and.05`	✅
`sll`	`tb_decode.sll.01`	✅
	`tb_decode.sll.02`	✅
	`tb_decode.sll.03`	✅
	`tb_decode.sll.04`	✅
	`tb_decode.sll.05`	✅
`srl`	`tb_decode.srl.01`	✅
	`tb_decode.srl.02`	✅
	`tb_decode.srl.03`	✅
	`tb_decode.srl.04`	✅
	`tb_decode.srl.05`	✅
`sra`	`tb_decode.sra.01`	✅
	`tb_decode.sra.02`	✅
	`tb_decode.sra.03`	✅
	`tb_decode.sra.04`	✅
	`tb_decode.sra.05`	✅
`bubble`	`tb_decode.bubble.01`	✅
	`tb_decode.bubble.02`	✅
	`tb_decode.bubble.03`	✅
	`tb_decode.bubble.04`	✅
	`tb_decode.bubble.05`	✅
`pipeline_wait`	`tb_decode.pipeline_wait.01`	✅
	`tb_decode.pipeline_wait.02`	✅
	`tb_decode.pipeline_wait.03`	✅
	`tb_decode.pipeline_wait.04`	✅
	`tb_decode.pipeline_wait.05`	✅
`hazard`	`tb_decode.hazard.01`	✅
	`tb_decode.hazard.02`	✅
	`tb_decode.hazard.03`	✅
	`tb_decode.hazard.04`	✅
	`tb_decode.hazard.05`	✅
`tb_hazard`	`reset`	`tb_hazard.reset.01`	✅
	`reset`	`tb_hazard.reset.02`	✅
	`control`	`tb_hazard.control.01`	✅
	`data`	`tb_hazard.data.X0_01`	✅
		`tb_hazard.data.PORT1_01`	✅
		`tb_hazard.data.PORT2_01`	✅
		`tb_hazard.data.MULTIPLE_01`	✅
`tb_loadstore_w_slave`	`no_stall`	`tb_loadstore_w_slave.no_stall.LW_01`	✅
		`tb_loadstore_w_slave.no_stall.LW_02`	✅
		`tb_loadstore_w_slave.no_stall.LW_03`	✅
		`tb_loadstore_w_slave.no_stall.LW_04`	✅
		`tb_loadstore_w_slave.no_stall.SW_01`	✅
		`tb_loadstore_w_slave.no_stall.SW_02`	✅
		`tb_loadstore_w_slave.no_stall.SW_03`	✅
		`tb_loadstore_w_slave.no_stall.SW_04`	✅
`tb_fetch`	`reset`	`tb_fetch.reset.01`	✅
		`tb_fetch.reset.02`	✅
		`tb_fetch.reset.03`	✅
	`no_stall`	`tb_fetch.no_stall.01`	✅
		`tb_fetch.no_stall.02`	✅
		`tb_fetch.no_stall.03`	✅
		`tb_fetch.no_stall.04`	✅
	`memory_stall`	`tb_fetch.memory_stall.01`	✅
		`tb_fetch.memory_stall.02`	✅
		`tb_fetch.memory_stall.03`	✅
	`memory_wait`	`tb_fetch.memory_wait.01`	✅
		`tb_fetch.memory_wait.02`	✅
		`tb_fetch.memory_wait.03`	✅
	`pipeline_wait`	`tb_fetch.pipeline_wait.01`	✅
		`tb_fetch.pipeline_wait.02`	✅
		`tb_fetch.pipeline_wait.03`	✅
		`tb_fetch.pipeline_wait.04`	✅
	`jump_after_reset`	`tb_fetch.jump_after_reset.01`	✅
	`jump_after_reset`	`tb_fetch.jump_after_reset.02`	✅
	`jump_during_ack`	`tb_fetch.jump_during_ack.01`	✅
	`jump_during_ack`	`tb_fetch.jump_during_ack.02`	✅
	`jump_during_wait`	`tb_fetch.jump_during_wait.01`	✅
	`jump_during_wait`	`tb_fetch.jump_during_wait.02`	✅
	`jump_during_memory_stall`	`tb_fetch.jump_during_memory_stall.01`	✅
	`jump_during_memory_stall`	`tb_fetch.jump_during_memory_stall.02`	✅
	`jump_on_output_handshake`	`tb_fetch.jump_on_output_handshake.01`	✅
	`jump_on_output_handshake`	`tb_fetch.jump_on_output_handshake.02`	✅
	`jump_during_pipeline_wait`	`tb_fetch.jump_during_pipeline_wait.01`	✅
	`jump_during_pipeline_wait`	`tb_fetch.jump_during_pipeline_wait.02`	✅
	`jump_back_to_back`	`tb_fetch.jump_back_to_back.01`	✅
	`jump_back_to_back`	`tb_fetch.jump_back_to_back.02`	✅
	`precedence_branch`	`tb_fetch.precedence_branch.01`	✅
	`precedence_increment`	`tb_fetch.precedence_increment.01`	✅
`tb_ecap5_dproc`	`nop`	`tb_ecap5_dproc.nop.01`	✅
		`tb_ecap5_dproc.nop.02`	✅
		`tb_ecap5_dproc.nop.03`	✅
		`tb_ecap5_dproc.nop.04`	✅
		`tb_ecap5_dproc.nop.05`	✅
		`tb_ecap5_dproc.nop.06`	✅
		`tb_ecap5_dproc.nop.07`	✅
	`alu`	`tb_ecap5_dproc.alu.01`	✅
		`tb_ecap5_dproc.alu.02`	✅
		`tb_ecap5_dproc.alu.03`	✅
		`tb_ecap5_dproc.alu.04`	✅
		`tb_ecap5_dproc.alu.05`	✅
		`tb_ecap5_dproc.alu.06`	✅
		`tb_ecap5_dproc.alu.07`	✅
	`ls_enable`	`tb_ecap5_dproc.ls_enable.01`	✅
		`tb_ecap5_dproc.ls_enable.02`	✅
		`tb_ecap5_dproc.ls_enable.03`	✅
		`tb_ecap5_dproc.ls_enable.04`	✅
		`tb_ecap5_dproc.ls_enable.05`	✅
		`tb_ecap5_dproc.ls_enable.06`	✅
		`tb_ecap5_dproc.ls_enable.07`	✅
		`tb_ecap5_dproc.ls_enable.08`	✅
	`branch`	`tb_ecap5_dproc.branch.01`	✅
		`tb_ecap5_dproc.branch.02`	✅
		`tb_ecap5_dproc.branch.03`	✅
		`tb_ecap5_dproc.branch.04`	✅
		`tb_ecap5_dproc.branch.05`	✅
		`tb_ecap5_dproc.branch.06`	✅
		`tb_ecap5_dproc.branch.07`	✅
		`tb_ecap5_dproc.branch.08`	✅
		`tb_ecap5_dproc.branch.09`	✅
	`data_hazard`	`tb_ecap5_dproc.data_hazard.01`	✅
		`tb_ecap5_dproc.data_hazard.02`	✅
		`tb_ecap5_dproc.data_hazard.03`	✅
		`tb_ecap5_dproc.data_hazard.04`	✅
`tb_memory`	`reset`	`tb_memory.reset.01`	✅
		`tb_memory.reset.02`	✅
		`tb_memory.reset.03`	✅
	`port1_read`	`tb_memory.port1_read.01`	✅
		`tb_memory.port1_read.02`	✅
		`tb_memory.port1_read.03`	✅
		`tb_memory.port1_read.04`	✅
	`port1_write`	`tb_memory.port1_write.01`	✅
		`tb_memory.port1_write.02`	✅
		`tb_memory.port1_write.03`	✅
		`tb_memory.port1_write.04`	✅
	`port2_read`	`tb_memory.port2_read.01`	✅
		`tb_memory.port2_read.02`	✅
		`tb_memory.port2_read.03`	✅
		`tb_memory.port2_read.04`	✅
	`port2_write`	`tb_memory.port2_write.01`	✅
		`tb_memory.port2_write.02`	✅
		`tb_memory.port2_write.03`	✅
		`tb_memory.port2_write.04`	✅
	`two_during_one`	`tb_memory.two_during_one.01`	✅
		`tb_memory.two_during_one.02`	✅
		`tb_memory.two_during_one.03`	✅
		`tb_memory.two_during_one.04`	✅
		`tb_memory.two_during_one.05`	✅
	`one_during_two`	`tb_memory.one_during_two.01`	✅
		`tb_memory.one_during_two.02`	✅
		`tb_memory.one_during_two.03`	✅
		`tb_memory.one_during_two.04`	✅
		`tb_memory.one_during_two.05`	✅
	`priority`	`tb_memory.priority.01`	✅
		`tb_memory.priority.02`	✅
		`tb_memory.priority.03`	✅
		`tb_memory.priority.04`	✅
		`tb_memory.priority.05`	✅
	`master_stall_s1`	`tb_memory.master_stall_s1.01`	✅
		`tb_memory.master_stall_s1.02`	✅
		`tb_memory.master_stall_s1.03`	✅
		`tb_memory.master_stall_s1.04`	✅
	`master_stall_s2`	`tb_memory.master_stall_s2.01`	✅
		`tb_memory.master_stall_s2.02`	✅
		`tb_memory.master_stall_s2.03`	✅
		`tb_memory.master_stall_s2.04`	✅
	`back_to_back`	`tb_memory.back_to_back.01`	✅
		`tb_memory.back_to_back.02`	✅
		`tb_memory.back_to_back.03`	✅
		`tb_memory.back_to_back.04`	✅
		`tb_memory.back_to_back.05`	✅
`tb_execute`	`reset`	`tb_execute.reset.01`	✅
		`tb_execute.reset.02`	✅
		`tb_execute.reset.03`	✅
		`tb_execute.reset.04`	✅
	`alu`	`tb_execute.alu.ADD_01`	✅
		`tb_execute.alu.ADD_02`	✅
		`tb_execute.alu.ADD_03`	✅
		`tb_execute.alu.SUB_01`	✅
		`tb_execute.alu.SUB_02`	✅
		`tb_execute.alu.SUB_03`	✅
		`tb_execute.alu.XOR_01`	✅
		`tb_execute.alu.XOR_02`	✅
		`tb_execute.alu.XOR_03`	✅
		`tb_execute.alu.OR_01`	✅
		`tb_execute.alu.OR_02`	✅
		`tb_execute.alu.OR_03`	✅
		`tb_execute.alu.AND_01`	✅
		`tb_execute.alu.AND_02`	✅
		`tb_execute.alu.AND_03`	✅
		`tb_execute.alu.SLT_01`	✅
		`tb_execute.alu.SLT_02`	✅
		`tb_execute.alu.SLT_03`	✅
		`tb_execute.alu.SLTU_01`	✅
		`tb_execute.alu.SLTU_02`	✅
		`tb_execute.alu.SLTU_03`	✅
		`tb_execute.alu.SLL_01`	✅
		`tb_execute.alu.SLL_02`	✅
		`tb_execute.alu.SLL_03`	✅
		`tb_execute.alu.SRL_01`	✅
		`tb_execute.alu.SRL_02`	✅
		`tb_execute.alu.SRL_03`	✅
		`tb_execute.alu.SRA_01`	✅
		`tb_execute.alu.SRA_02`	✅
		`tb_execute.alu.SRA_03`	✅
	`branch`	`tb_execute.branch.BEQ_01`	✅
		`tb_execute.branch.BEQ_02`	✅
		`tb_execute.branch.BEQ_03`	✅
		`tb_execute.branch.BNE_01`	✅
		`tb_execute.branch.BNE_02`	✅
		`tb_execute.branch.BNE_03`	✅
		`tb_execute.branch.BLT_01`	✅
		`tb_execute.branch.BLT_02`	✅
		`tb_execute.branch.BLT_03`	✅
		`tb_execute.branch.BLTU_01`	✅
		`tb_execute.branch.BLTU_02`	✅
		`tb_execute.branch.BLTU_03`	✅
		`tb_execute.branch.BGE_01`	✅
		`tb_execute.branch.BGE_02`	✅
		`tb_execute.branch.BGE_03`	✅
		`tb_execute.branch.BGEU_01`	✅
		`tb_execute.branch.BGEU_02`	✅
		`tb_execute.branch.BGEU_03`	✅
		`tb_execute.branch.JALR_01`	✅
		`tb_execute.branch.JALR_02`	✅
		`tb_execute.branch.JALR_03`	✅
	`back_to_back`	`tb_execute.back_to_back.01`	✅
		`tb_execute.back_to_back.02`	✅
		`tb_execute.back_to_back.03`	✅
	`bubble`	`tb_execute.bubble.01`	✅
		`tb_execute.bubble.02`	✅
		`tb_execute.bubble.03`	✅
	`pipeline_wait_after_reset`	`tb_execute.pipeline_wait_after_reset.01`	✅
		`tb_execute.pipeline_wait_after_reset.02`	✅
		`tb_execute.pipeline_wait_after_reset.03`	✅
`tb_execute.pipeline_wait_after_reset.04`		✅
`pipeline_wait`	`tb_execute.pipeline_wait.01`	✅
	`tb_execute.pipeline_wait.02`	✅
	`tb_execute.pipeline_wait.03`	✅
	`tb_execute.pipeline_wait.04`	✅
`hazard`	`tb_execute.hazard.01`	✅
	`tb_execute.hazard.02`	✅
	`tb_execute.hazard.03`	✅

Skipped tests

riscv-tests.fence_i.01

riscv-tests.fence_i.02

riscv-tests.ma_data.01

riscv-tests.ma_data.02

Traceability report

	Covered	Untraceable	Uncovered	Total
Requirements	89	5	3	97

Covered requirements

Requirement	Description	Derived from	Covered by	Tested by
User Requirements
`U_INSTRUCTION_SET_01`	ECAP5-DPROC shall implement the RV32I instruction set.		F_REGISTER_01 F_REGISTER_02 F_REGISTER_03 F_INSTR_IMMEDIATE_01 F_INSTR_IMMEDIATE_02 F_INSTR_IMMEDIATE_03 F_OPCODE_ENCODING_01 F_OPCODE_ENCODING_02 F_OPCODE_ENCODING_03 F_OPCODE_ENCODING_04 F_OPCODE_ENCODING_05 F_OPCODE_ENCODING_06 F_LUI_01 F_AUIPC_01 F_JAL_01 F_JAL_02 F_JALR_01 F_JALR_02 F_BEQ_01 F_BNE_01 F_BLT_01 F_BGE_01 F_BLTU_01 F_BGEU_01 F_LB_01 F_LH_01 F_LW_01 F_LBU_01 F_LHU_01 F_SB_01 F_SH_01 F_SW_01 F_ADDI_01 F_SLTI_01 F_SLTIU_01 F_XORI_01 F_ORI_01 F_ANDI_01 F_SLLI_01 F_SRLI_01 F_SRAI_01 F_ADD_01 F_SUB_01 F_SLT_01 F_SLTU_01 F_XOR_01 F_OR_01 F_AND_01 F_SLL_01 F_SRL_01 F_SRA_01 F_INSTR_ADDR_MISALIGNED_01 F_MISALIGNED_MEMORY_ACCESS_01 F_MEMORY_INTERFACE_01
`U_MEMORY_INTERFACE_01`	ECAP5-DPROC shall access both instruction and data through a unique memory interface.		`A_FUNCTIONAL_PARTITIONING_01`
`U_MEMORY_INTERFACE_02`	ECAP5-DPROC's unique memory interface shall be compliant with the Wishbone specification.		`F_WISHBONE_DATASHEET_01 F_WISHBONE_RESET_01 F_WISHBONE_RESET_02 F_WISHBONE_RESET_03 F_WISHBONE_TRANSFER_CYCLE_01 F_WISHBONE_TRANSFER_CYCLE_02 F_WISHBONE_TRANSFER_CYCLE_03 F_WISHBONE_HANDSHAKE_02 F_WISHBONE_STALL_01 F_WISHBONE_READ_CYCLE_01 F_WISHBONE_READ_CYCLE_02 F_WISHBONE_WRITE_CYCLE_01 F_WISHBONE_WRITE_CYCLE_02 F_WISHBONE_TIMING_01`
`U_RESET_01`	ECAP5-DPROC shall provide a signal which shall hold ECAP5-DPROC in a reset state while asserted.		`I_RESET_01`
`U_BOOT_ADDRESS_01`	The address at which ECAP5-DPROC jumps after the reset signal is deasserted shall be hardware-configurable.		`F_REGISTER_RESET_01`
External Interface Requirements
`I_RESET_01`	The rst_i signal shall hold ECAP5-DPROC in a reset state while asserted.	`U_RESET_01`		`tb_hazard.reset.01 tb_hazard.reset.02 tb_loadstore.reset.01 tb_loadstore.reset.02 tb_execute.reset.01 tb_execute.reset.02 tb_execute.reset.03 tb_execute.reset.04 tb_memory.reset.01 tb_memory.reset.02 tb_memory.reset.03 tb_fetch.reset.01 tb_fetch.reset.02 tb_fetch.reset.03 tb_decode.reset.01`
Functional Requirements
`F_REGISTER_01`	ECAP5-DPROC shall implement 32 user-accessible general purpose registers ranging from x0 to x31.	`U_INSTRUCTION_SET_01`		`tb_registers.read_x0.01 tb_registers.read_port_a.01 tb_registers.read_port_b.01 tb_registers.write_x0.01 tb_registers.write.01 tb_registers.parallel_read.01 tb_registers.read_before_write.01`
`F_REGISTER_02`	Register x0 shall always be equal to zero.	`U_INSTRUCTION_SET_01`		`tb_registers.read_x0.01 tb_registers.write_x0.01`
`F_REGISTER_03`	ECAP5-DPROC shall implement a pc register storing the address of the current instruction.	`U_INSTRUCTION_SET_01`		tb_fetch.no_stall.01 tb_fetch.no_stall.02 tb_fetch.no_stall.03 tb_fetch.no_stall.04 tb_fetch.memory_stall.01 tb_fetch.memory_stall.02 tb_fetch.memory_stall.03 tb_fetch.memory_wait.01 tb_fetch.memory_wait.02 tb_fetch.memory_wait.03 tb_fetch.pipeline_wait.01 tb_fetch.pipeline_wait.02 tb_fetch.pipeline_wait.03 tb_fetch.pipeline_wait.04 tb_fetch.jump_after_reset.01 tb_fetch.jump_after_reset.02 tb_fetch.jump_during_ack.01 tb_fetch.jump_during_ack.02 tb_fetch.jump_during_wait.01 tb_fetch.jump_during_wait.02 tb_fetch.jump_during_memory_stall.01 tb_fetch.jump_during_memory_stall.02 tb_fetch.jump_on_output_handshake.01 tb_fetch.jump_on_output_handshake.02 tb_fetch.jump_during_pipeline_wait.01 tb_fetch.jump_during_pipeline_wait.02 tb_fetch.jump_back_to_back.01 tb_fetch.jump_back_to_back.02 tb_fetch.precedence_branch.01 tb_fetch.precedence_increment.01
`F_REGISTER_RESET_01`	The pc register shall be loaded with an hardware-configurable address when ECAP5-DPROC leaves its reset state.	`U_BOOT_ADDRESS_01`		`tb_fetch.no_stall.02`
`F_INSTR_IMMEDIATE_01`	Immediate values shall be sign-extended.	`U_INSTRUCTION_SET_01`		tb_execute.branch.BEQ_02 tb_execute.branch.BNE_02 tb_execute.branch.BLT_02 tb_execute.branch.BLTU_02 tb_execute.branch.BGE_02 tb_execute.branch.BGEU_02 tb_decode.jal.01 tb_decode.jalr.01 tb_decode.beq.03 tb_decode.bne.03 tb_decode.blt.03 tb_decode.bge.03 tb_decode.bltu.03 tb_decode.bgeu.03 tb_decode.lb.01 tb_decode.lbu.01 tb_decode.lh.01 tb_decode.lhu.01 tb_decode.lw.01 tb_decode.sb.01 tb_decode.sh.01 tb_decode.sw.01 tb_decode.addi.01 tb_decode.slti.01 tb_decode.sltiu.01 tb_decode.xori.01 tb_decode.ori.01 tb_decode.andi.01 tb_decode.slli.01 tb_decode.srli.01 tb_decode.srai.01
`F_INSTR_IMMEDIATE_02`	The value of an instruction immediate shall be the concatenation of immediate fragments from the instruction encoding.	`U_INSTRUCTION_SET_01`		`tb_decode.lui.01 tb_decode.auipc.01 tb_decode.jal.01 tb_decode.jalr.01 tb_decode.beq.03 tb_decode.bne.03 tb_decode.blt.03 tb_decode.bge.03 tb_decode.bltu.03 tb_decode.bgeu.03 tb_decode.lb.01 tb_decode.lbu.01 tb_decode.lh.01 tb_decode.lhu.01 tb_decode.lw.01 tb_decode.sb.01 tb_decode.sh.01 tb_decode.sw.01 tb_decode.addi.01 tb_decode.slti.01 tb_decode.sltiu.01 tb_decode.xori.01 tb_decode.ori.01 tb_decode.andi.01 tb_decode.slli.01 tb_decode.srli.01 tb_decode.srai.01`
`F_INSTR_IMMEDIATE_03`	Missing immediate fragments shall be replaced by zeros.	`U_INSTRUCTION_SET_01`		`tb_decode.lui.01 tb_decode.auipc.01 tb_decode.jal.01 tb_decode.jalr.01 tb_decode.beq.03 tb_decode.bne.03 tb_decode.blt.03 tb_decode.bge.03 tb_decode.bltu.03 tb_decode.bgeu.03 tb_decode.lb.01 tb_decode.lbu.01 tb_decode.lh.01 tb_decode.lhu.01 tb_decode.lw.01 tb_decode.sb.01 tb_decode.sh.01 tb_decode.sw.01 tb_decode.addi.01 tb_decode.slti.01 tb_decode.sltiu.01 tb_decode.xori.01 tb_decode.ori.01 tb_decode.andi.01 tb_decode.slli.01 tb_decode.srli.01 tb_decode.srai.01`
`F_OPCODE_ENCODING_01`	Instructions with the following opcodes shall be decoded as an R-type instruction : OP.	`U_INSTRUCTION_SET_01`		tb_decode.add.01 tb_decode.add.02 tb_decode.add.03 tb_decode.add.04 tb_decode.add.05 tb_decode.sub.01 tb_decode.sub.02 tb_decode.sub.03 tb_decode.sub.04 tb_decode.sub.05 tb_decode.slt.01 tb_decode.slt.02 tb_decode.slt.03 tb_decode.slt.04 tb_decode.slt.05 tb_decode.sltu.01 tb_decode.sltu.02 tb_decode.sltu.03 tb_decode.sltu.04 tb_decode.sltu.05 tb_decode.xor.01 tb_decode.xor.02 tb_decode.xor.03 tb_decode.xor.04 tb_decode.xor.05 tb_decode.or.01 tb_decode.or.02 tb_decode.or.03 tb_decode.or.04 tb_decode.or.05 tb_decode.and.01 tb_decode.and.02 tb_decode.and.03 tb_decode.and.04 tb_decode.and.05 tb_decode.sll.01 tb_decode.sll.02 tb_decode.sll.03 tb_decode.sll.04 tb_decode.sll.05 tb_decode.srl.01 tb_decode.srl.02 tb_decode.srl.03 tb_decode.srl.04 tb_decode.srl.05 tb_decode.sra.01 tb_decode.sra.02 tb_decode.sra.03 tb_decode.sra.04 tb_decode.sra.05
`F_OPCODE_ENCODING_02`	Instructions with the following opcodes shall be decoded as an I-type instruction : JALR, LOAD, OP-IMM, MISC-MEM and SYSTEM.	`U_INSTRUCTION_SET_01`		tb_decode.jalr.01 tb_decode.jalr.02 tb_decode.jalr.03 tb_decode.jalr.04 tb_decode.jalr.05 tb_decode.lb.01 tb_decode.lb.02 tb_decode.lb.03 tb_decode.lb.04 tb_decode.lb.05 tb_decode.lbu.01 tb_decode.lbu.02 tb_decode.lbu.03 tb_decode.lbu.04 tb_decode.lbu.05 tb_decode.lh.01 tb_decode.lh.02 tb_decode.lh.03 tb_decode.lh.04 tb_decode.lh.05 tb_decode.lhu.01 tb_decode.lhu.02 tb_decode.lhu.03 tb_decode.lhu.04 tb_decode.lhu.05 tb_decode.lw.01 tb_decode.lw.02 tb_decode.lw.03 tb_decode.lw.04 tb_decode.lw.05 tb_decode.addi.01 tb_decode.addi.02 tb_decode.addi.03 tb_decode.addi.04 tb_decode.addi.05 tb_decode.slti.01 tb_decode.slti.02 tb_decode.slti.03 tb_decode.slti.04 tb_decode.slti.05 tb_decode.sltiu.01 tb_decode.sltiu.02 tb_decode.sltiu.03 tb_decode.sltiu.04 tb_decode.sltiu.05 tb_decode.xori.01 tb_decode.xori.02 tb_decode.xori.03 tb_decode.xori.04 tb_decode.xori.05 tb_decode.ori.01 tb_decode.ori.02 tb_decode.ori.03 tb_decode.ori.04 tb_decode.ori.05 tb_decode.andi.01 tb_decode.andi.02 tb_decode.andi.03 tb_decode.andi.04 tb_decode.andi.05 tb_decode.slli.01 tb_decode.slli.02 tb_decode.slli.03 tb_decode.slli.04 tb_decode.slli.05 tb_decode.srli.01 tb_decode.srli.02 tb_decode.srli.03 tb_decode.srli.04 tb_decode.srli.05 tb_decode.srai.01 tb_decode.srai.02 tb_decode.srai.03 tb_decode.srai.04 tb_decode.srai.05
`F_OPCODE_ENCODING_03`	Instructions with the following opcodes shall be decoded as an S-type instruction : STORE.	`U_INSTRUCTION_SET_01`		`tb_decode.sb.01 tb_decode.sb.02 tb_decode.sb.03 tb_decode.sb.04 tb_decode.sb.05 tb_decode.sh.01 tb_decode.sh.02 tb_decode.sh.03 tb_decode.sh.04 tb_decode.sh.05 tb_decode.sw.01 tb_decode.sw.02 tb_decode.sw.03 tb_decode.sw.04 tb_decode.sw.05`
`F_OPCODE_ENCODING_04`	Instructions with the following opcodes shall be decoded as an B-type instruction : BRANCH.	`U_INSTRUCTION_SET_01`		tb_decode.beq.01 tb_decode.beq.02 tb_decode.beq.03 tb_decode.beq.04 tb_decode.beq.05 tb_decode.beq.06 tb_decode.bne.01 tb_decode.bne.02 tb_decode.bne.03 tb_decode.bne.04 tb_decode.bne.05 tb_decode.bne.06 tb_decode.blt.01 tb_decode.blt.02 tb_decode.blt.03 tb_decode.blt.04 tb_decode.blt.05 tb_decode.blt.06 tb_decode.bge.01 tb_decode.bge.02 tb_decode.bge.03 tb_decode.bge.04 tb_decode.bge.05 tb_decode.bge.06 tb_decode.bltu.01 tb_decode.bltu.02 tb_decode.bltu.03 tb_decode.bltu.04 tb_decode.bltu.05 tb_decode.bltu.06 tb_decode.bgeu.01 tb_decode.bgeu.02 tb_decode.bgeu.03 tb_decode.bgeu.04 tb_decode.bgeu.05 tb_decode.bgeu.06
`F_OPCODE_ENCODING_05`	Instructions with the following opcodes shall be decoded as an U-type instruction : LUI and AUIPC.	`U_INSTRUCTION_SET_01`		`tb_decode.lui.01 tb_decode.lui.02 tb_decode.lui.03 tb_decode.lui.04 tb_decode.lui.05 tb_decode.auipc.01 tb_decode.auipc.02 tb_decode.auipc.03 tb_decode.auipc.04 tb_decode.auipc.05`
`F_OPCODE_ENCODING_06`	Instructions with the following opcodes shall be decoded as an J-type instruction : JAL.	`U_INSTRUCTION_SET_01`		`tb_decode.jal.01 tb_decode.jal.02 tb_decode.jal.03 tb_decode.jal.04 tb_decode.jal.05`
`F_LUI_01`	When the opcode is LUI, the register pointed by the rd field shall be loaded with the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.lui.01 riscv-tests.lui.02`
`F_AUIPC_01`	When the opcode is AUIPC, the register pointed by the rd field shall be the signed sum of the immediate value and the address of the instruction.	`U_INSTRUCTION_SET_01`		`riscv-tests.auipc.01 riscv-tests.auipc.02`
`F_JAL_01`	When the opcode is JAL, the pc register shall be loaded with the signed sum of the immediate value and the address of the instruction.	`U_INSTRUCTION_SET_01`		`riscv-tests.jal.01 riscv-tests.jal.02`
`F_JAL_02`	When the opcode is JAL, the register pointed by the rd field shall be loaded with the address of the instruction incremented by 4.	`U_INSTRUCTION_SET_01`		`riscv-tests.jal.01 riscv-tests.jal.02`
`F_JALR_01`	When the opcode is JALR and the func3 field is 0x0, the pc register shall be loaded with the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.jalr.01 riscv-tests.jalr.02`
`F_JALR_02`	When the opcode is JALR and the func3 field is 0x0, the register pointed by the rd field shall be loaded with the address of the instruction incremented by 4.	`U_INSTRUCTION_SET_01`		`riscv-tests.jalr.01 riscv-tests.jalr.02`
`F_BEQ_01`	When the opcode is BRANCH and the func3 field is 0x0, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the registers pointed by the rs1 field and the rs2 field are equal.	`U_INSTRUCTION_SET_01`		`riscv-tests.beq.01 riscv-tests.beq.02`
`F_BNE_01`	When the opcode is BRANCH and the func3 field is 0x1, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the registers pointed by the rs1 field and the rs2 field are equal.	`U_INSTRUCTION_SET_01`		`riscv-tests.bne.01 riscv-tests.bne.02`
`F_BLT_01`	When the opcode is BRANCH and the func3 field is 0x4, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using a signed comparison.	`U_INSTRUCTION_SET_01`		`riscv-tests.blt.01 riscv-tests.blt.02`
`F_BGE_01`	When the opcode is BRANCH and the func3 field is 0x5, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is greater than the register pointed by the rs2 field using a signed comparison.	`U_INSTRUCTION_SET_01`		`riscv-tests.bge.01 riscv-tests.bge.02`
`F_BLTU_01`	When the opcode is BRANCH and the func3 field is 0x6, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using an unsigned comparison.	`U_INSTRUCTION_SET_01`		`riscv-tests.bltu.01 riscv-tests.bltu.02`
`F_BGEU_01`	When the opcode is BRANCH and the func3 field is 0x7, the pc register shall be loaded with the signed sum of the address of the instruction and the immediate value, if the register pointed by the rs1 field is greater than the register pointed by the rs2 field using an unsigned comparison.	`U_INSTRUCTION_SET_01`		`riscv-tests.bgeu.01 riscv-tests.bgeu.02`
`F_LB_01`	When the opcode is LOAD and the func3 field is 0x0, the register pointed by the rd field shall be the 32 bits sign-extended 8-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.lb.01 riscv-tests.lb.02`
`F_LH_01`	When the opcode is LOAD and the func3 field is 0x1, the register pointed by the rd field shall be the 32 bits sign-extended 16-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.lh.01 riscv-tests.lh.02`
`F_LW_01`	When the opcode is LOAD and the func3 field is 0x2, the register pointed by the rd field shall be the 32-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.lw.01 riscv-tests.lw.02`
`F_LBU_01`	When the opcode is LOAD and the func3 field is 0x4, the register pointed by the rd field shall be the 32 bits zero-extended 8-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.lbu.01 riscv-tests.lbu.02`
`F_LHU_01`	When the opcode is LOAD and the func3 field is 0x5, the register pointed by the rd field shall be the 32 bits zero-extended 16-bit value stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.lhu.01 riscv-tests.lhu.02`
`F_SB_01`	When the opcode is STORE and the func3 field is 0x0, the least-significant byte of the register pointed by the rs2 field shall be stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.sb.01 riscv-tests.sb.02`
`F_SH_01`	When the opcode is STORE and the func3 field is 0x1, the two least-significant bytes of the register pointed by the rs2 field shall be stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.sh.01 riscv-tests.sh.02`
`F_SW_01`	When the opcode is STORE and the func3 field is 0x2, the register pointed by the rs2 field shall be stored in memory at the address specified by the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.sw.01 riscv-tests.sw.02`
`F_ADDI_01`	When the opcode is OP-IMM and the func3 field is 0x0, the register pointed by the rd field shall be loaded with the signed sum of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.addi.01 riscv-tests.addi.02`
`F_SLTI_01`	When the opcode is OP-IMM and the func3 field is 0x1, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the immediate value using a signed comparison, 0 otherwise.	`U_INSTRUCTION_SET_01`		`riscv-tests.slti.01 riscv-tests.slti.02`
`F_SLTIU_01`	When the opcode is OP-IMM and the func3 field is 0x3, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the immediate value using an unsigned comparison, 0 otherwise.	`U_INSTRUCTION_SET_01`		`riscv-tests.sltiu.01 riscv-tests.sltiu.02`
`F_XORI_01`	When the opcode is OP-IMM and the func3 field is 0x4, the register pointed by the rd field shall be the result of a bitwise xor of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.xori.01 riscv-tests.xori.02`
`F_ORI_01`	When the opcode is OP-IMM and the func3 field is 0x6, the register pointed by the rd field shall be the result of a bitwise or of the register pointed by the rs1 field and the immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.ori.01 riscv-tests.ori.02`
`F_ANDI_01`	When the opcode is OP-IMM and the func3 field is 0x7, the register pointed by the rd field shall be the result of a bitwise and of the register pointed by the rs1 field and immediate value.	`U_INSTRUCTION_SET_01`		`riscv-tests.andi.01 riscv-tests.andi.02`
`F_SLLI_01`	When the opcode is OP-IMM and the func3 field is 0x1, the register pointed by the rd field shall be the register pointed by the rs1 field shited left by the number of bits specified in the 5 lowest-significant bits of the immediate value, filling lower bits with zeros.	`U_INSTRUCTION_SET_01`		`riscv-tests.slli.01 riscv-tests.slli.02`
`F_SRLI_01`	When the opcode is OP-IMM, the func3 field is 0x5 and the 30th bit of the immediate value is 0, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified in the 5 lowest-significant bits of the immediate value, filling upper bits with zeros.	`U_INSTRUCTION_SET_01`		`riscv-tests.srli.01 riscv-tests.srli.02`
`F_SRAI_01`	When the opcode is OP-IMM, the func3 field is 0x5 and the 30th bit of the immediate value is 1, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified in the 5 lowest-significant bits of the immediate value, filling upper bits with the most-significant bit of the register pointed by the rs1 field.	`U_INSTRUCTION_SET_01`		`riscv-tests.srai.01 riscv-tests.srai.02`
`F_ADD_01`	When the opcode is OP, the func3 field is 0x0 and the func7 field is 0x0, the register pointed by the rd field shall be the signed sum of the registers pointed by the rs1 and rs2 fields.	`U_INSTRUCTION_SET_01`		`riscv-tests.add.01 riscv-tests.add.02`
`F_SUB_01`	When the opcode is OP, the func3 field is 0x0 and the func7 field is 0x20, the register pointed by the rd field shall be the difference of the register pointed by the rs1 field minus the register pointed by the rs2 fields.	`U_INSTRUCTION_SET_01`		`riscv-tests.sub.01 riscv-tests.sub.02`
`F_SLT_01`	When the opcode is OP and the func3 field is 0x2, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using a signed comparison, 0 otherwise.	`U_INSTRUCTION_SET_01`		`riscv-tests.slt.01 riscv-tests.slt.02`
`F_SLTU_01`	When the opcode is OP and the func3 field is 0x3, the register pointed by the rd field shall be 1 if the register pointed by the rs1 field is lower than the register pointed by the rs2 field using an unsigned comparison, 0 otherwise.	`U_INSTRUCTION_SET_01`		`riscv-tests.sltu.01 riscv-tests.sltu.02`
`F_XOR_01`	When the opcode is OP and the func3 field is 0x4, the register pointed by the rd field shall be the result of a bitwise xor of the registers pointed by the rs1 and rs2 fields.	`U_INSTRUCTION_SET_01`		`riscv-tests.xor.01 riscv-tests.xor.02`
`F_OR_01`	When the opcode is OP and the func3 field is 0x6, the register pointed by the rd field shall be the result of a bitwise or of the registers pointed by the rs1 and rs2 fields.	`U_INSTRUCTION_SET_01`		`riscv-tests.or.01 riscv-tests.or.02`
`F_AND_01`	When the opcode is OP and the func3 field is 0x7, the register pointed by the rd field shall be the result of a bitwise and of the registers pointed by the rs1 and rs2 fields.	`U_INSTRUCTION_SET_01`		`riscv-tests.and.01 riscv-tests.and.02`
`F_SLL_01`	When the opcode is OP and the func3 field is 0x1, the register pointed by the rd field shall be the register pointed by the rs1 field shited left by the number of bits specified by the register pointed by the rs2 field, filling lower bits with zeros.	`U_INSTRUCTION_SET_01`		`riscv-tests.sll.01 riscv-tests.sll.02`
`F_SRL_01`	When the opcode is OP, the func3 field is 0x5 and the func7 field is 0x0, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified by the register pointed by the rs2 field, filling upper bits with zeros.	`U_INSTRUCTION_SET_01`		`riscv-tests.srl.01 riscv-tests.srl.02`
`F_SRA_01`	When the opcode is OP, the func3 field is 0x5 and the func7 field is 0x0, the register pointed by the rd field shall be the register pointed by the rs1 field shited right by the number of bits specified in the register pointed by the rs2 field, filling upper bits with the most-significant bit of the register pointed by the rs1 field.	`U_INSTRUCTION_SET_01`		`riscv-tests.sra.01 riscv-tests.sra.02`
`F_WISHBONE_RESET_01`	The memory interface shall initialize itself at the rising edge of clk_i following the assertion of rst_i.	`U_MEMORY_INTERFACE_02`		`tb_memory.reset.01 tb_memory.reset.02 tb_memory.reset.03`
`F_WISHBONE_RESET_02`	The memory interface shall stay in the initialization state until the rising edge of clk_i following the deassertion of rst_i.	`U_MEMORY_INTERFACE_02`		`tb_memory.reset.01 tb_memory.reset.02 tb_memory.reset.03`
`F_WISHBONE_RESET_03`	Signals wb_stb_o and wb_cyc_o shall be deasserted while the memory interface is in the initialization state. The state of all other memory interface signals are undefined in response to a reset cycle.	`U_MEMORY_INTERFACE_02`		`tb_memory.reset.01 tb_memory.reset.02 tb_memory.reset.03`
`F_WISHBONE_TRANSFER_CYCLE_01`	The memory interface shall assert wb_cyc_o for the entire duration of the memory access.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_read.04 tb_memory.port1_write.04 tb_memory.port2_read.04 tb_memory.port2_write.04`
`F_WISHBONE_TRANSFER_CYCLE_02`	Signal wb_cyc_o shall be asserted no later than the rising edge of clk_i that qualifies the assertion of wb_stb_o.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_read.04 tb_memory.port1_write.04 tb_memory.port2_read.04 tb_memory.port2_write.04`
`F_WISHBONE_TRANSFER_CYCLE_03`	Signal wb_cyc_o shall be deasserted no earlier than the rising edge of clk_i that qualifies the deassertion of wb_stb_o.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_read.04 tb_memory.port1_write.04 tb_memory.port2_read.04 tb_memory.port2_write.04`
`F_WISHBONE_HANDSHAKE_02`	The memory interface must qualify the following signals with wb_stb_o : wb_adr_o, wb_dat_o, wb_sel_o and wb_we_o.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_read.04 tb_memory.port1_write.04 tb_memory.port2_read.04 tb_memory.port2_write.04`
`F_WISHBONE_STALL_01`	While initiating a request, the memory interface shall hold the state of its outputs until wb_stall_i is deasserted.	`U_MEMORY_INTERFACE_02`		`tb_memory.master_stall_s1.04 tb_memory.master_stall_s2.04`
`F_WISHBONE_READ_CYCLE_01`	A read transaction shall be started by asserting both wb_cyc_o and wb_stb_i, and deasserting wb_we_o.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_read.04 tb_memory.port2_read.04`
`F_WISHBONE_READ_CYCLE_02`	The memory interface shall conform to the READ cycle detailed in the figure below.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_read.04 tb_memory.port2_read.04`
`F_WISHBONE_WRITE_CYCLE_01`	A write transaction shall be started by asserting wb_cyc_o, wb stb i and wb_we_o.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_write.04 tb_memory.port2_write.04`
`F_WISHBONE_WRITE_CYCLE_02`	The memory interface shall conform to the WRITE cycle detailed in figure below.	`U_MEMORY_INTERFACE_02`		`tb_memory.port1_write.04 tb_memory.port2_write.04`
Architecture Requirements
`A_FUNCTIONAL_PARTITIONING_01`	The memory module shall arbitrate memory requests from both the fetch module and the loadstore module.	`U_MEMORY_INTERFACE_01`		tb_memory.port1_read.01 tb_memory.port1_read.02 tb_memory.port1_read.03 tb_memory.port1_read.04 tb_memory.port1_write.01 tb_memory.port1_write.02 tb_memory.port1_write.03 tb_memory.port1_write.04 tb_memory.port2_read.01 tb_memory.port2_read.02 tb_memory.port2_read.03 tb_memory.port2_read.04 tb_memory.port2_write.01 tb_memory.port2_write.02 tb_memory.port2_write.03 tb_memory.port2_write.04 tb_memory.two_during_one.01 tb_memory.two_during_one.02 tb_memory.two_during_one.03 tb_memory.two_during_one.04 tb_memory.two_during_one.05 tb_memory.one_during_two.01 tb_memory.one_during_two.02 tb_memory.one_during_two.03 tb_memory.one_during_two.04 tb_memory.one_during_two.05 tb_memory.priority.01 tb_memory.priority.02 tb_memory.priority.03 tb_memory.priority.04 tb_memory.priority.05 tb_memory.master_stall_s1.01 tb_memory.master_stall_s1.02 tb_memory.master_stall_s1.03 tb_memory.master_stall_s1.04 tb_memory.master_stall_s2.01 tb_memory.master_stall_s2.02 tb_memory.master_stall_s2.03 tb_memory.master_stall_s2.04 tb_memory.back_to_back.01 tb_memory.back_to_back.02 tb_memory.back_to_back.03 tb_memory.back_to_back.04 tb_memory.back_to_back.05
`A_MEMORY_01`	The memory module shall give priority access to the external memory bus for the fetch module.			`tb_memory.priority.01 tb_memory.priority.02 tb_memory.priority.03 tb_memory.priority.04 tb_memory.priority.05`
`A_FUNCTIONAL_PARTITIONING_02`	The fetch module shall implement the instruction fetch stage of the pipeline.			tb_fetch.no_stall.01 tb_fetch.no_stall.02 tb_fetch.no_stall.03 tb_fetch.no_stall.04 tb_fetch.memory_stall.01 tb_fetch.memory_stall.02 tb_fetch.memory_stall.03 tb_fetch.memory_wait.01 tb_fetch.memory_wait.02 tb_fetch.memory_wait.03 tb_fetch.pipeline_wait.01 tb_fetch.pipeline_wait.02 tb_fetch.pipeline_wait.03 tb_fetch.pipeline_wait.04 tb_fetch.jump_after_reset.01 tb_fetch.jump_after_reset.02 tb_fetch.jump_during_ack.01 tb_fetch.jump_during_ack.02 tb_fetch.jump_during_wait.01 tb_fetch.jump_during_wait.02 tb_fetch.jump_during_memory_stall.01 tb_fetch.jump_during_memory_stall.02 tb_fetch.jump_on_output_handshake.01 tb_fetch.jump_on_output_handshake.02 tb_fetch.jump_during_pipeline_wait.01 tb_fetch.jump_during_pipeline_wait.02 tb_fetch.jump_back_to_back.01 tb_fetch.jump_back_to_back.02 tb_fetch.precedence_branch.01 tb_fetch.precedence_increment.01
`A_FUNCTIONAL_PARTITIONING_03`	The decode module shall implement the decode stage of the pipeline.			tb_decode.lui.01 tb_decode.lui.02 tb_decode.lui.03 tb_decode.lui.04 tb_decode.lui.05 tb_decode.auipc.01 tb_decode.auipc.02 tb_decode.auipc.03 tb_decode.auipc.04 tb_decode.auipc.05 tb_decode.jal.01 tb_decode.jal.02 tb_decode.jal.03 tb_decode.jal.04 tb_decode.jal.05 tb_decode.jalr.01 tb_decode.jalr.02 tb_decode.jalr.03 tb_decode.jalr.04 tb_decode.jalr.05 tb_decode.beq.01 tb_decode.beq.02 tb_decode.beq.03 tb_decode.beq.04 tb_decode.beq.05 tb_decode.beq.06 tb_decode.bne.01 tb_decode.bne.02 tb_decode.bne.03 tb_decode.bne.04 tb_decode.bne.05 tb_decode.bne.06 tb_decode.blt.01 tb_decode.blt.02 tb_decode.blt.03 tb_decode.blt.04 tb_decode.blt.05 tb_decode.blt.06 tb_decode.bge.01 tb_decode.bge.02 tb_decode.bge.03 tb_decode.bge.04 tb_decode.bge.05 tb_decode.bge.06 tb_decode.bltu.01 tb_decode.bltu.02 tb_decode.bltu.03 tb_decode.bltu.04 tb_decode.bltu.05 tb_decode.bltu.06 tb_decode.bgeu.01 tb_decode.bgeu.02 tb_decode.bgeu.03 tb_decode.bgeu.04 tb_decode.bgeu.05 tb_decode.bgeu.06 tb_decode.lb.01 tb_decode.lb.02 tb_decode.lb.03 tb_decode.lb.04 tb_decode.lb.05 tb_decode.lbu.01 tb_decode.lbu.02 tb_decode.lbu.03 tb_decode.lbu.04 tb_decode.lbu.05 tb_decode.lh.01 tb_decode.lh.02 tb_decode.lh.03 tb_decode.lh.04 tb_decode.lh.05 tb_decode.lhu.01 tb_decode.lhu.02 tb_decode.lhu.03 tb_decode.lhu.04 tb_decode.lhu.05 tb_decode.lw.01 tb_decode.lw.02 tb_decode.lw.03 tb_decode.lw.04 tb_decode.lw.05 tb_decode.sb.01 tb_decode.sb.02 tb_decode.sb.03 tb_decode.sb.04 tb_decode.sb.05 tb_decode.sh.01 tb_decode.sh.02 tb_decode.sh.03 tb_decode.sh.04 tb_decode.sh.05 tb_decode.sw.01 tb_decode.sw.02 tb_decode.sw.03 tb_decode.sw.04 tb_decode.sw.05 tb_decode.addi.01 tb_decode.addi.02 tb_decode.addi.03 tb_decode.addi.04 tb_decode.addi.05 tb_decode.slti.01 tb_decode.slti.02 tb_decode.slti.03 tb_decode.slti.04 tb_decode.slti.05 tb_decode.sltiu.01 tb_decode.sltiu.02 tb_decode.sltiu.03 tb_decode.sltiu.04 tb_decode.sltiu.05 tb_decode.xori.01 tb_decode.xori.02 tb_decode.xori.03 tb_decode.xori.04 tb_decode.xori.05 tb_decode.ori.01 tb_decode.ori.02 tb_decode.ori.03 tb_decode.ori.04 tb_decode.ori.05 tb_decode.andi.01 tb_decode.andi.02 tb_decode.andi.03 tb_decode.andi.04 tb_decode.andi.05 tb_decode.slli.01 tb_decode.slli.02 tb_decode.slli.03 tb_decode.slli.04 tb_decode.slli.05 tb_decode.srli.01 tb_decode.srli.02 tb_decode.srli.03 tb_decode.srli.04 tb_decode.srli.05 tb_decode.srai.01 tb_decode.srai.02 tb_decode.srai.03 tb_decode.srai.04 tb_decode.srai.05 tb_decode.add.01 tb_decode.add.02 tb_decode.add.03 tb_decode.add.04 tb_decode.add.05 tb_decode.sub.01 tb_decode.sub.02 tb_decode.sub.03 tb_decode.sub.04 tb_decode.sub.05 tb_decode.slt.01 tb_decode.slt.02 tb_decode.slt.03 tb_decode.slt.04 tb_decode.slt.05 tb_decode.sltu.01 tb_decode.sltu.02 tb_decode.sltu.03 tb_decode.sltu.04 tb_decode.sltu.05 tb_decode.xor.01 tb_decode.xor.02 tb_decode.xor.03 tb_decode.xor.04 tb_decode.xor.05 tb_decode.or.01 tb_decode.or.02 tb_decode.or.03 tb_decode.or.04 tb_decode.or.05 tb_decode.and.01 tb_decode.and.02 tb_decode.and.03 tb_decode.and.04 tb_decode.and.05 tb_decode.sll.01 tb_decode.sll.02 tb_decode.sll.03 tb_decode.sll.04 tb_decode.sll.05 tb_decode.srl.01 tb_decode.srl.02 tb_decode.srl.03 tb_decode.srl.04 tb_decode.srl.05 tb_decode.sra.01 tb_decode.sra.02 tb_decode.sra.03 tb_decode.sra.04 tb_decode.sra.05 tb_decode.bubble.01 tb_decode.bubble.02 tb_decode.bubble.03 tb_decode.bubble.04 tb_decode.bubble.05 tb_decode.pipeline_wait.01 tb_decode.pipeline_wait.02 tb_decode.pipeline_wait.03 tb_decode.pipeline_wait.04 tb_decode.pipeline_wait.05 tb_decode.hazard.01 tb_decode.hazard.02 tb_decode.hazard.03 tb_decode.hazard.04 tb_decode.hazard.05
`A_FUNCTIONAL_PARTITIONING_04`	The register module shall implement the internal general-purpose registers.			`tb_registers.read_x0.01 tb_registers.read_port_a.01 tb_registers.read_port_b.01 tb_registers.write_x0.01 tb_registers.write.01 tb_registers.parallel_read.01 tb_registers.read_before_write.01`
`A_FUNCTIONAL_PARTITIONING_05`	The execute module shall implement the execute stage of the pipeline.			tb_execute.alu.ADD_01 tb_execute.alu.ADD_02 tb_execute.alu.ADD_03 tb_execute.alu.SUB_01 tb_execute.alu.SUB_02 tb_execute.alu.SUB_03 tb_execute.alu.XOR_01 tb_execute.alu.XOR_02 tb_execute.alu.XOR_03 tb_execute.alu.OR_01 tb_execute.alu.OR_02 tb_execute.alu.OR_03 tb_execute.alu.AND_01 tb_execute.alu.AND_02 tb_execute.alu.AND_03 tb_execute.alu.SLT_01 tb_execute.alu.SLT_02 tb_execute.alu.SLT_03 tb_execute.alu.SLTU_01 tb_execute.alu.SLTU_02 tb_execute.alu.SLTU_03 tb_execute.alu.SLL_01 tb_execute.alu.SLL_02 tb_execute.alu.SLL_03 tb_execute.alu.SRL_01 tb_execute.alu.SRL_02 tb_execute.alu.SRL_03 tb_execute.alu.SRA_01 tb_execute.alu.SRA_02 tb_execute.alu.SRA_03 tb_execute.branch.BEQ_01 tb_execute.branch.BEQ_02 tb_execute.branch.BEQ_03 tb_execute.branch.BNE_01 tb_execute.branch.BNE_02 tb_execute.branch.BNE_03 tb_execute.branch.BLT_01 tb_execute.branch.BLT_02 tb_execute.branch.BLT_03 tb_execute.branch.BLTU_01 tb_execute.branch.BLTU_02 tb_execute.branch.BLTU_03 tb_execute.branch.BGE_01 tb_execute.branch.BGE_02 tb_execute.branch.BGE_03 tb_execute.branch.BGEU_01 tb_execute.branch.BGEU_02 tb_execute.branch.BGEU_03 tb_execute.back_to_back.01 tb_execute.back_to_back.02 tb_execute.back_to_back.03 tb_execute.bubble.01 tb_execute.bubble.02 tb_execute.bubble.03 tb_execute.pipeline_wait_after_reset.01 tb_execute.pipeline_wait_after_reset.02 tb_execute.pipeline_wait_after_reset.03 tb_execute.pipeline_wait_after_reset.04 tb_execute.pipeline_wait.01 tb_execute.pipeline_wait.02 tb_execute.pipeline_wait.03 tb_execute.pipeline_wait.04 tb_execute.reset.01 tb_execute.reset.02 tb_execute.reset.03 tb_execute.reset.04 tb_execute.branch.JALR_01 tb_execute.branch.JALR_02 tb_execute.branch.JALR_03 tb_execute.hazard.01 tb_execute.hazard.02 tb_execute.hazard.03
`A_FUNCTIONAL_PARTITIONING_06`	The loadstore module shall implement the load/store stage of the pipeline.			tb_loadstore.no_stall.LB_01 tb_loadstore.no_stall.LB_02 tb_loadstore.no_stall.LB_03 tb_loadstore.no_stall.LB_04 tb_loadstore.no_stall.LB_05 tb_loadstore.no_stall.LBU_01 tb_loadstore.no_stall.LBU_02 tb_loadstore.no_stall.LBU_03 tb_loadstore.no_stall.LBU_04 tb_loadstore.no_stall.LBU_05 tb_loadstore.no_stall.LH_01 tb_loadstore.no_stall.LH_02 tb_loadstore.no_stall.LH_03 tb_loadstore.no_stall.LH_04 tb_loadstore.no_stall.LH_05 tb_loadstore.no_stall.LHU_01 tb_loadstore.no_stall.LHU_02 tb_loadstore.no_stall.LHU_03 tb_loadstore.no_stall.LHU_04 tb_loadstore.no_stall.LHU_05 tb_loadstore.no_stall.LW_01 tb_loadstore.no_stall.LW_02 tb_loadstore.no_stall.LW_03 tb_loadstore.no_stall.LW_04 tb_loadstore.no_stall.LW_05 tb_loadstore.no_stall.SB_01 tb_loadstore.no_stall.SB_02 tb_loadstore.no_stall.SB_03 tb_loadstore.no_stall.SB_04 tb_loadstore.no_stall.SB_05 tb_loadstore.no_stall.SH_01 tb_loadstore.no_stall.SH_02 tb_loadstore.no_stall.SH_03 tb_loadstore.no_stall.SH_04 tb_loadstore.no_stall.SH_05 tb_loadstore.no_stall.SW_01 tb_loadstore.no_stall.SW_02 tb_loadstore.no_stall.SW_03 tb_loadstore.no_stall.SW_04 tb_loadstore.no_stall.SW_05 tb_loadstore.memory_stall.01 tb_loadstore.memory_stall.02 tb_loadstore.memory_stall.03 tb_loadstore.memory_wait.01 tb_loadstore.memory_wait.02 tb_loadstore.memory_wait.03 tb_loadstore.bypass.01 tb_loadstore.bypass.02 tb_loadstore.bypass.03 tb_loadstore.bubble.01 tb_loadstore.bubble.02 tb_loadstore.bubble.03 tb_loadstore.back_to_back.01 tb_loadstore.back_to_back.02 tb_loadstore_w_slave.no_stall.LW_01 tb_loadstore_w_slave.no_stall.LW_02 tb_loadstore_w_slave.no_stall.LW_03 tb_loadstore_w_slave.no_stall.LW_04 tb_loadstore_w_slave.no_stall.SW_01 tb_loadstore_w_slave.no_stall.SW_02 tb_loadstore_w_slave.no_stall.SW_03 tb_loadstore_w_slave.no_stall.SW_04
`A_FUNCTIONAL_PARTITIONING_07`	The writeback module shall implement the write-back stage of the pipeline.			`tb_writeback.write.01 tb_writeback.bypass.01 tb_writeback.bubble.01`
`A_WRITEBACK_01`	The writeback module shall perform its operation in a single cycle.			`tb_writeback.write.01 tb_writeback.bypass.01 tb_writeback.bubble.01`
`A_FUNCTIONAL_PARTITIONING_08`	The hazard module shall handle the detection of data and control hazards as well as trigger the associated pipeline stalls and pipeline drops.			`tb_hazard.control.01 tb_hazard.data.X0_01 tb_hazard.data.PORT1_01 tb_hazard.data.PORT2_01 tb_hazard.data.MULTIPLE_01`
`A_PIPELINE_WAIT_01`	The following modules shall implement the pipeline wait state : fetch, decode, execute.			tb_execute.pipeline_wait_after_reset.01 tb_execute.pipeline_wait_after_reset.02 tb_execute.pipeline_wait_after_reset.03 tb_execute.pipeline_wait_after_reset.04 tb_execute.pipeline_wait.01 tb_execute.pipeline_wait.02 tb_execute.pipeline_wait.03 tb_execute.pipeline_wait.04 tb_fetch.pipeline_wait.01 tb_fetch.pipeline_wait.02 tb_fetch.pipeline_wait.03 tb_fetch.pipeline_wait.04 tb_decode.pipeline_wait.01 tb_decode.pipeline_wait.02 tb_decode.pipeline_wait.03 tb_decode.pipeline_wait.04 tb_decode.pipeline_wait.05
`A_PIPELINE_BUBBLE_01`	The following modules shall implement the pipeline bubble state : decode, execute, loadstore and writeback.			`tb_loadstore.bubble.01 tb_loadstore.bubble.02 tb_loadstore.bubble.03 tb_execute.bubble.01 tb_execute.bubble.02 tb_execute.bubble.03 tb_writeback.bubble.01 tb_decode.bubble.01 tb_decode.bubble.02 tb_decode.bubble.03 tb_decode.bubble.04 tb_decode.bubble.05`
`A_PIPELINE_STALL_01`	The fetch module shall stall the pipeline while performing the memory request. The pipeline shall be unstalled after completing the request.			`tb_fetch.no_stall.04 tb_fetch.memory_stall.03 tb_fetch.memory_wait.03 tb_fetch.pipeline_wait.04`
`A_PIPELINE_STALL_02`	The loadstore module shall stall the pipeline while performing the memory request. The pipeline shall be unstalled after completing the request.			`tb_loadstore.no_stall.LB_05 tb_loadstore.no_stall.LBU_05 tb_loadstore.no_stall.LH_05 tb_loadstore.no_stall.LHU_05 tb_loadstore.no_stall.LW_05 tb_loadstore.no_stall.SB_05 tb_loadstore.no_stall.SH_05 tb_loadstore.no_stall.SW_05 tb_loadstore.memory_stall.03 tb_loadstore.memory_wait.03`
`A_HAZARD_01`	The hazard module shall issue a stall request to the decode module while a write operation to one of the next registers to be read by decode is to be performed by the following modules : decode (current output), execute, loadstore and writeback.			`tb_hazard.data.X0_01 tb_hazard.data.PORT1_01 tb_hazard.data.PORT2_01 tb_hazard.data.MULTIPLE_01`
`A_PIPELINE_STALL_03`	The decode module shall stall the pipeline upon stall request from the hazard module.			`tb_decode.hazard.01 tb_decode.hazard.02 tb_decode.hazard.03 tb_decode.hazard.04 tb_decode.hazard.05`
`A_PIPELINE_STALL_04`	While stalling the pipeline due to a stall request from the hazard module, the decode module shall clear its register outputs.			`tb_decode.hazard.03`
`A_HAZARD_02`	The hazard module shall issue a pipeline drop request to the execute module on the rising edge of clk_i after the execute module has issued a branch request to the fetch module. The pipeline drop request shall be held asserted for two cycles.			`tb_hazard.control.01`
`A_PIPELINE_DROP_01`	The execute module shall discard the decode module's output and output a pipeline bubble upon drop request from the hazard module.			`tb_execute.hazard.01 tb_execute.hazard.02 tb_execute.hazard.03`

Untraceable requirements

Requirement	Description	Derived from	Justification
External Interface Requirements
`I_CLK_01`	ECAP5-DPROC's outputs shall be registered on the rising edge of clk_i.		This requirement is covered by the hdl code.
Functional Requirements
`F_MEMORY_INTERFACE_01`	Both instruction and data accesses shall be handled by a unique external memory interface.	`U_INSTRUCTION_SET_01`	This requirement is covered by the hdl code of the memory module.
`F_WISHBONE_DATASHEET_01`	The memory interface shall comply with the Wishbone Datasheet provided in section 2.1.	`U_MEMORY_INTERFACE_02`	This requirement is covered by the hdl code.
`F_WISHBONE_TIMING_01`	The clock input clk_i shall coordinate all activites for the internal logic within the memory interface. All output signals of the memory interface shall be registered at the rising edge of clk_i. All input signals of the memory interface shall be stable before the rising edge of clk_i.	`U_MEMORY_INTERFACE_02`	This requirement is covered by the hdl code.
Architecture Requirements
`A_CLOCK_DOMAIN_01`	All modules of ECAP5-DPROC shall belong to a unique clock domain.		This requirement is covered by the hdl code.

Uncovered requirements

Requirement	Description	Derived from
User Requirements
`U_DEBUG_01`	ECAP5-DPROC shall be compliant with the RISC-V External Debug Support specification.
Functional Requirements
`F_INSTR_ADDR_MISALIGNED_01`	An Instruction Address Misaligned exception shall be raised when the target address of a taken branch or an unconditional jump is not four-byte aligned.	`U_INSTRUCTION_SET_01`
`F_MISALIGNED_MEMORY_ACCESS_01`	A Misaligned Memory Access exception shall be raised when the target address of a load/store instruction is not aligned on the referenced type size.	`U_INSTRUCTION_SET_01`

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