2. Overall Description
2.1. User needs
ECAP5 is the primary user for ECAP5-DWBUART, but it could be used as a standalone Wishbone UART peripheral as well.
2.1.1. Serial Interface
| ID | U_UART_01 |
| Description | The peripheral shall perform parallel-to-serial conversion of the provided data. |
| ID | U_UART_02 |
| Description | The peripheral shall perform serial-to-parallel conversion of the received data. |
| ID | U_UART_03 |
| Description | The peripheral shall support full-duplex communications. |
| ID | U_UART_04 |
| Description | The peripheral shall detect parity errors. |
| ID | U_UART_05 |
| Description | The peripheral shall detect framing errors. |
| ID | U_UART_06 |
| Description | The peripheral shall detect overrrun errors. |
2.1.2. Configuration
| ID | U_BAUD_RATE_01 |
| Description | The baud rate of the peripheral shall be software-configurable. |
| ID | U_BAUD_RATE_02 |
| Description | The following baudrates shall be tested to be within 2% tolerance : 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600, 1000000, 2000000, 3000000. |
| ID | U_PARITY_BIT_01 |
| Description | The parity bit of the peripheral shall be software-configurable. |
| ID | U_DATA_SIZE_01 |
| Description | The data packet size of the peripheral shall be software-configurable. |
| ID | U_STOP_BIT_01 |
| Description | The stop bits of the peripheral shall be software-configurable. |
UART flow control is not supported in version 1.0.0.
2.1.3. Memory-Mapped Interface
| ID | U_REGISTERS_01 |
| Description | The peripheral shall provide memory-mapped configuration and status registers. |
| ID | U_MEMORY_INTERFACE_01 |
| Description | The peripheral memory-mapped registers shall be accessible through a memory interface compliant with the Wishbone specification. |
Description |
Specification |
|---|---|
Revision level of the WISHBONE specification |
B4 |
Type of interface |
SLAVE |
Signal names for the WISHBONE interface |
Wishbone signals are prefixed with |
ERR_I support |
No |
RTY_I support |
No |
Supported tags |
None |
Port size |
32-bit |
Port granularity |
8-bit |
Maximum operand size |
32-bit |
Data transfer ordering |
Little Endian |
Sequence of data transfer |
Undefined |
Clock constraints |
Clocked on clk_i |
2.2. Assumptions and Dependencies
N/A