3. Requirements
3.1. External Interface Requirements
Name |
Type |
Width |
Description |
|---|---|---|---|
clk_i |
I |
1 |
Clock input. |
rst_i |
I |
1 |
Hardware reset. |
Name |
Type |
Width |
Description |
|---|---|---|---|
wb_adr_i |
I |
32 |
The address output array is used to pass binary address. |
wb_dat_i |
I |
32 |
The data input array is used to pass binary data. |
wb_dat_o |
O |
32 |
The data output array is used to pass binary data. |
wb_sel_i |
I |
4 |
The select output array indicates where valid data is expected on the wb_dat_i signal array during READ cycles, and where it is placed on the wb_dat_o signal array during WRITE cycles. Each individual select signal correlates to one of four active bytes on the 32-bit data port. |
wb_we_i |
I |
1 |
The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. This signal is negated during READ cycles and is asserted during WRITE cycles. |
wb_stb_i |
I |
1 |
The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface. |
wb_ack_o |
O |
1 |
The acknowledge input, when asserted, indicates the normal termination of a bus cycle. |
wb_cyc_i |
I |
1 |
The cycle output, when asserted, indicates that a valid bus cycle is in progress. This signal is asserted for the duration of all bus cycles. |
wb_stall_o |
O |
1 |
The stall input indicates that current slave is not able to accept the transfer in the transaction queue. |
Name |
Type |
Width |
Description |
|---|---|---|---|
uart_rx_i |
I |
1 |
This signal is sampled by the peripheral to receive data |
uart_tx_o |
O |
1 |
This signal is driven by the peripheral to send data |
3.2. Functional Requirements
| ID | F_RESET_01 |
| Description | The registers shall all be reset to 0 when rst_i is asserted. |
| Derived from |
| ID | F_RESET_02 |
| Description | The uart_tx_o signal shall be asserted while rst_i is asserted. |
| Derived from |
3.2.1. Memory interface
Note
The wishbone protocol is not specified here as this module is expected to use ECAP5-DWBMMSC as its wishbone interface.
3.2.1.1. Memory-mapped registers
| ID | F_REGISTERS_01 |
| Description | The following registers shall be implemented and accessible through the wishbone memory interface. |
| Derived from |
Address Offset |
Register name |
Width (in bits) |
Access |
Reset value |
Section/page |
|---|---|---|---|---|---|
0000_0000h |
Status register (UART_SR) |
32 |
R |
0000_0000h |
|
0000_0004h |
Control register (UART_CR) |
32 |
R/W |
0000_0000h |
|
0000_0008h |
Receive Data register (UART_RXDR) |
32 |
R |
0000_0000h |
|
0000_000Ch |
Transmit Data register (UART_TXDR) |
32 |
W |
0000_0000h |
3.2.1.1.1. Status register (UART_SR)
Position |
Field |
Description |
|---|---|---|
31-5 |
Reserved |
This field is reserved. This read-only field is reserved and always has the value 0. |
4 |
PE |
Parity Error This bit is cleared after reading it. 0 No parity error 1 Parity error detected |
3 |
FE |
Framing Error This bit is cleared after reading it. 0 No framing error 1 Framing error detected |
2 |
RXOE |
Receive Overrun Error This bit is cleared after reading it. 0 No received overrun error 1 A packet was received but RXNE is asserted |
1 |
TXE |
Transmit register Empty 0 The transmit register is full (being sent) 1 The transmit register is empty |
0 |
RXNE |
Receive register Not Empty 0 The receive register is empty (no data) 1 The receive register is not empty empty |
3.2.1.1.2. Control register (UART_CR)
UART_CR contains the control for selecting the UART baudrate, parity, size and stop bits.
Position |
Field |
Description |
|---|---|---|
31-16 |
ACC_INCR |
Accumulator increment/Baudrate selector The specified accumulator increment determines the baud rate with the formula ACC_INCR = round(baudrate * 2^15 / freq). |
15-4 |
reserved |
This field is reserved. This read-only field is reserved and always has the value 0. |
3 |
DS |
Data Size selector 0 7-bit data 1 8-bit data |
2 |
S |
Stop bit selector 0 1 stop bit 1 2 stop bits |
1-0 |
P |
Parity bit selector 00 No parity checks 01 Odd parity 10 Even parity 11 reserved |
3.2.1.1.3. Receive Data register (UART_RXDR)
Position |
Field |
Description |
|---|---|---|
31-8 |
reserved |
This field is reserved. This read-only field is reserved and always has the value 0. |
7-0 |
RXD |
Receive Data The received data is written to this field. The field is cleared by hardware after being read. |
3.2.1.1.4. Transmit Data register (UART_TXDR)
Position |
Field |
Description |
|---|---|---|
31-8 |
reserved |
This field is reserved. |
7-0 |
TXD |
Transmit Data Data written to this field is sent through the serial link. The TXE field of the UART_SR shall be sample before writing again to this field to prevent data loss. |
| ID | F_READ_01 |
| Description | The UART_RXDR register shall be reset after being read and the RXNE field of UART_SR shall be deasserted. |
| Derived from |
| ID | F_READ_02 |
| Description | The following fields of UART_SR shall be reset after being read : PE, FE and RXOE. |
| Derived from |
| ID | F_RESET_03 |
| Description | Any change to UART_CR shall cancel both ongoing tranmissions and receptions. |
| Derived from |
3.2.2. Serial protocol
| ID | F_UART_01 |
| Description | The following frame format shall be used to encode and decode transit/receive data. |
| Derived from |
| ID | F_UART_02 |
| Description | The number of data bits, parity bits and stop bits shall match the configuration provided in UART_CR. |
| Derived from |
| ID | F_UART_03 |
| Description | The time Tbr shall be equal to the product of the CLK_DIV field of UART_CR with the period of clk_i. |
| Derived from |
| ID | F_UART_04 |
| Description | Parallel transmission/reception shall be supported. |
| Derived from |
3.2.3. Receive
| ID | F_RECEIVE_01 |
| Description | The peripheral shall sample the uart_rx_i signal with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. |
| Derived from |
| ID | F_RECEIVE_02 |
| Description | The peripheral shall set the value of the RXD field of UART_RXDR after latching the stop bit. |
| Derived from |
| ID | F_RECEIVE_03 |
| Description | The peripheral shall assert the RXNE field of UART_SR when setting the value of the RXD field. |
| Derived from |
| ID | F_RECEIVE_ERROR_01 |
| Description | The peripheral shall assert the PE field of UART_SR when the result of the xor of all the received bits is not equal to the received parity bit. |
| Derived from |
| ID | F_RECEIVE_ERROR_02 |
| Description | The peripheral shall assert the FE field of UART_SR when the received stop bit is zero instead of one. |
| Derived from |
| ID | F_RECEIVE_ERROR_03 |
| Description | The peripheral shall assert the RXOE field of UART_SR after latching the stop bit while the RXNE field of UART_SR is asserted. |
| Derived from |
3.2.4. Transmit
| ID | F_TRANSMIT_01 |
| Description | The peripheral shall transmit the TXD field of UART_TXDR after a write to UART_TXDR when the TXE field of UART_SR is deasserted, with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. |
| Derived from |
3.3. Non-functional Requirements
N/A