ECAP5-DWBUART
User guide
Memory Map and Registers
Status register (UART_SR)
Control register (UART_CR)
Receive Data register (UART_RXDR)
Transmit Data register (UART_TXDR)
Specifications
Specification Document
1. Introduction
1.1. Purpose
1.2. Intended Audience and Use
1.3. Product Scope
1.4. Conventions
1.4.1. Requirement format
1.5. Definitions and Abbreviations
1.6. References
2. Overall Description
2.1. User needs
2.1.1. Serial Interface
2.1.2. Configuration
2.1.3. Memory-Mapped Interface
2.2. Assumptions and Dependencies
3. Requirements
3.1. External Interface Requirements
3.2. Functional Requirements
3.2.1. Memory interface
3.2.1.1. Memory-mapped registers
3.2.1.1.1. Status register (UART_SR)
3.2.1.1.2. Control register (UART_CR)
3.2.1.1.3. Receive Data register (UART_RXDR)
3.2.1.1.4. Transmit Data register (UART_TXDR)
3.2.2. Serial protocol
3.2.3. Receive
3.2.4. Transmit
3.3. Non-functional Requirements
4. Configuration
4.1. Instanciation parameters
5. Architecture Overview
ECAP5-DWBUART
Specification Document
5.
Architecture Overview
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5.
Architecture Overview
